CN-121979362-A - Method, device and interface circuit for parallel output of multiple paths of serial data

CN121979362ACN 121979362 ACN121979362 ACN 121979362ACN-121979362-A

Abstract

The application relates to the technical field of digital signal processing and integrated circuits, and provides a method, a device and an interface circuit for multi-channel serial data parallel output. The method comprises the steps of transmitting a plurality of data and at least one clock associated with the plurality of data through a plurality of data paths, generating a plurality of effective flag signals corresponding to the plurality of effective data one by one, generating a plurality of groups of selection control signals corresponding to the plurality of output interfaces one by one based on data identifications and mapping relations of the plurality of effective data, and respectively controlling a data signal selector, a clock signal selector and an enabling signal selector associated with the plurality of output interfaces through the plurality of groups of selection control signals. Therefore, the occupation of resources and the consumption of circuit area are reduced, and the reliability and the instantaneity of data output are improved.

Inventors

Tian yuntong
LU YUCHEN
WANG LANLAN
WEI YUNTONG

Assignees

光梓信息科技（上海）有限公司

Dates

Publication Date: 20260505
Application Date: 20260403

Claims (20)

1. A method for multiple serial data parallel output, the method comprising: Transmitting a plurality of data and at least one clock associated with the plurality of data through a plurality of data lanes, wherein the plurality of data includes a plurality of valid data, a maximum number of the plurality of valid data is not higher than a number of a plurality of output interfaces, and a mapping relationship indicates that the plurality of valid data is allocated to the plurality of output interfaces separately and not repeatedly; Generating a plurality of valid flag signals corresponding to the plurality of valid data one by one, and generating a plurality of groups of selection control signals corresponding to the plurality of output interfaces one by one based on the data identifications and the mapping relations of the valid data, wherein the time sequence relations among the valid level segments of the valid flag signals are consistent with the time sequence relations among the valid data, each group of selection control signals is composed of a data selection signal, a clock selection signal and an enabling selection signal, and The data signal selector, the clock signal selector and the enable signal selector respectively associated with the plurality of output interfaces are controlled by the plurality of groups of selection control signals, and the plurality of data paths are used as the input of the data signal selector and the clock signal selector respectively associated with the plurality of output interfaces, and the plurality of valid flag signals are used as the input of the enable signal selector respectively associated with the plurality of output interfaces.
2. The method of claim 1, wherein a given output interface is any one of the plurality of output interfaces, a given one of the plurality of sets of selection control signals corresponding to the given output interface, a data selection signal of the given selection control signal for controlling a data signal selector associated with the given output interface to select a data signal line for transmitting given valid data allocated to the given output interface from the plurality of data paths, a clock selection signal of the given selection control signal for controlling the clock signal selector associated with the given output interface to select a clock signal line for transmitting a given clock associated with the given valid data from the plurality of data paths, and an enable selection signal of the given selection control signal for controlling an enable signal selector associated with the given output interface to select a given valid flag signal corresponding to the given valid data from the plurality of valid flag signals.
3. The method of claim 2, wherein the output of the given output interface associated enable signal selector is used to enable or disable the output of the given output interface associated clock signal selector to thereby derive the given output interface associated register clock signal, and wherein the given output interface associated register clock signal is used to trigger the output of the given output interface associated data signal selector.
4. A method according to claim 3, wherein the output of the given output interface associated enable signal selector is provided as an input to a control terminal of the given output interface associated latch circuit, and the output of the given output interface associated clock signal selector is provided as an input to a signal terminal of the given output interface associated latch circuit, and the given output interface associated register clock signal is provided as an output of the given output interface associated latch circuit.
5. A method according to claim 3, wherein the output of the given output interface associated enable signal selector is provided as an input to a control terminal of the given output interface associated gating circuit, the output of the given output interface associated clock signal selector is provided as an input to a signal terminal of the given output interface associated gating circuit, and the given output interface associated register clock signal is provided as an output of the given output interface associated gating circuit.
6. A method according to claim 3, wherein the register clock signal associated with the given output interface is provided as an input to a control terminal of the flip-flop circuit associated with the given output interface and the output of the data signal selector associated with the given output interface is provided as an input to a signal terminal of the flip-flop circuit associated with the given output interface.
7. The method of claim 6, wherein the flip-flop circuit associated with the given output interface has a storage function and is operable to store data that is not less than a maximum data bit width of the plurality of valid data, and wherein the data signal selector associated with the given output interface has a dynamic output function and is operable to adapt the maximum data bit width of the plurality of valid data.
8. The method of claim 3, wherein the output of the clock signal selector associated with the given output interface is enabled when the output of the enable signal selector associated with the given output interface is an active level segment of the given active flag signal, and wherein the output of the clock signal selector associated with the given output interface is disabled when the output of the enable signal selector associated with the given output interface is not an active level segment of the given active flag signal.
9. The method of claim 8, wherein the active level segment of the given active flag signal is high for one or more clock cycles.
10. The method of claim 1, wherein the at least one clock is a single clock, and wherein the plurality of valid data share the single clock.
11. The method of claim 1, wherein the at least one clock comprises a plurality of clocks that are in one-to-one correspondence with the plurality of valid data, and wherein the frequencies of the plurality of clocks are each different.
12. The method of claim 1, wherein the allocated valid data for each of the plurality of output interfaces is stored in an output register for each of the plurality of output interfaces, wherein the output register for each of the plurality of output interfaces is configured to output the plurality of valid data in parallel based on a global output clock, and wherein an update order between the output registers for each of the plurality of output interfaces is consistent with a data transfer order between the plurality of valid data.
13. The method of claim 1, wherein the plurality of sets of selection control signals are generated by a selection signal generation module that is configurable so as not to generate a selection control signal corresponding to at least one of the plurality of output interfaces or an output of a data signal selector associated with the at least one output interface is an input to a D flip-flop and a reset signal of the D flip-flop is held active.
14. The method of claim 1, wherein the plurality of data belongs to a current batch, a next batch relative to the current batch is transmitted through the plurality of data paths for parallel output by the plurality of output interfaces, and the data transmission of the next batch begins at least after the data transmission of the current batch is completed.
15. The method of claim 14, further comprising changing the mapping relationship at least after the completion of the data transfer of the current batch and before the data transfer of the next batch.
16. The method of claim 1, wherein the plurality of data belongs to a current batch of a plurality of batches, the plurality of batches being respectively transmitted through the plurality of data paths for being respectively output in parallel by the plurality of output interfaces, the respective data of the plurality of batches including a corresponding batch identification, the plurality of output interfaces being configured to output all valid data of a same batch of the plurality of batches in parallel based on a global output clock in accordance with the batch identification of the respective data of the plurality of batches.
17. The method of claim 16, wherein data transmission of a next batch relative to the current batch begins before data transmission of the current batch is completed.
18. The method of claim 1, wherein the plurality of data paths are further configured to transmit at least one enable signal associated with the plurality of data, the valid flag signal corresponding to valid data associated with the at least one enable signal being generated based on the at least one enable signal.
19. An apparatus for multiple serial data parallel output, the apparatus comprising: A selection signal generation module for generating a plurality of effective flag signals corresponding to a plurality of effective data one-to-one, the timing relationship between effective level segments of the plurality of effective flag signals being identical to the timing relationship between the plurality of effective data, a plurality of data paths for transmitting a plurality of data and at least one clock associated with the plurality of data, the plurality of data including the plurality of effective data, the maximum number of the plurality of effective data being not higher than the number of a plurality of output interfaces, and the mapping relationship stored by the selection signal generation module indicating that the plurality of effective data are respectively and not repeatedly allocated to the plurality of output interfaces, and The selection signal generating module is further configured to generate a plurality of sets of selection control signals corresponding to the plurality of output interfaces one by one based on the data identifiers of the plurality of valid data and the mapping relation, and the plurality of sets of selection control signals respectively control the data signal selector, the clock signal selector and the enable signal selector associated with the plurality of output interfaces, and the plurality of data paths serve as inputs of the data signal selector and the clock signal selector associated with the plurality of output interfaces, and the plurality of valid flag signals serve as inputs of the enable signal selector associated with the plurality of output interfaces.
20. An interface circuit, the interface circuit comprising: A plurality of output interfaces, wherein the plurality of output interfaces are used for outputting a plurality of paths of serial data in parallel, a plurality of data paths are used for transmitting a plurality of data and at least one clock associated with the plurality of data, the plurality of data comprises a plurality of valid data as the plurality of paths of serial data, the maximum number of the plurality of valid data is not higher than the number of the plurality of output interfaces, and the mapping relation stored by the selection signal generating module indicates that the plurality of valid data are respectively and repeatedly distributed to the plurality of output interfaces; the selection signal generation module is used for generating a plurality of effective mark signals corresponding to the plurality of effective data one by one, the time sequence relation between the effective level segments of the effective mark signals is consistent with the time sequence relation between the effective data, and The selection signal generating module is further configured to generate a plurality of sets of selection control signals corresponding to the plurality of output interfaces one by one based on the data identifiers of the plurality of valid data and the mapping relation, and the plurality of sets of selection control signals respectively control the data signal selector, the clock signal selector and the enable signal selector associated with the plurality of output interfaces, and the plurality of data paths serve as inputs of the data signal selector and the clock signal selector associated with the plurality of output interfaces, and the plurality of valid flag signals serve as inputs of the enable signal selector associated with the plurality of output interfaces.

Description

Method, device and interface circuit for parallel output of multiple paths of serial data Technical Field The present application relates to the field of digital signal processing and integrated circuit technologies, and in particular, to a method, an apparatus, and an interface circuit for parallel output of multiple serial data. Background With the development of artificial intelligence large model technology and high-speed digital communication technology, higher requirements are put on high-performance memory and high-performance data transmission, and large-scale parallel output is often required to be realized after multiple paths of serial data are decoded. Multiple serial data transmitted according to the high speed serial data transmission standard, such as SERializer de-SERializer/DESerializer, SERDES and high speed peripheral component interconnect (PERIPHERAL COMPONENT INTERCONNECT EXPRESS, PCIe), are parsed for parallel output, such as double data rate synchronous dynamic random access memory (Double Data Rate Synchronous Dynamic Random Access Memory, DDR SDRAM) and high bandwidth memory (High Bandwidth Memory, HBM). The sender of the data may be from different devices, e.g. different PCIE devices, or from different machines, e.g. devices interconnected by SERDES technology, which means that there may be different clock frequencies between the multiple serial data, and that there may be frequency differences and phase differences from the sender of the multiple serial data to the receiver for parallel output. Therefore, in the application scenario of multiple serial output and parallel output, one challenge is how to overcome the frequency difference and phase difference faced by the data transmission across clock domains that may exist. One prior art approach is to absorb the frequency and phase differences by means of an asynchronous first-in first-out (First Input First Output, FIFO) memory, but this means that a separate asynchronous FIFO needs to be provided for each way of serial data, which leads to a higher memory resource requirement under the requirement of massive parallel output. In addition, in the application scenario of multiple serial output and parallel output, another challenge is how to implement configurable mapping between output interfaces and data, for example, one output interface corresponds to one path of serial data originally, and needs to be changed to another path of serial data corresponding to the output interface. One scheme in the prior art is to store all data in a register, and then implement configurable mapping between any output interface and any data path through a combinational logic switching selection circuit, which means that a large amount of storage resources are required to store the data, and complex combinational logic circuits are required to implement signal transmission across clock domains, and support complex cross-clock synchronous processing mechanisms or clock switching mechanisms. Therefore, the application provides a method, a device and an interface circuit for multi-channel serial data parallel output, which not only effectively reduce the occupation of resources and the consumption of circuit area, but also effectively overcome the problems of frequency difference and phase difference of cross-clock domain signal transmission, does not need a complex cross-clock synchronous processing mechanism or clock switching mechanism, is beneficial to reducing the risk of cross-clock transmission and metastable state risk caused by large-scale combinational logic, and is beneficial to improving the reliability and instantaneity of data output. Disclosure of Invention In a first aspect, the present application provides a method for multiple serial data parallel output. The method includes transmitting a plurality of data and at least one clock associated with the plurality of data through a plurality of data paths, wherein the plurality of data includes a plurality of valid data, a maximum number of the plurality of valid data is not higher than a number of a plurality of output interfaces, and a mapping relationship indicates that the plurality of valid data are respectively and non-repeatedly allocated to the plurality of output interfaces, generating a plurality of valid flag signals in one-to-one correspondence with the plurality of valid data, and generating a plurality of sets of selection control signals in one-to-one correspondence with the plurality of output interfaces based on respective data identifications of the plurality of valid data and the mapping relationship, wherein a timing relationship between respective valid level segments of the plurality of valid flag signals is consistent with a timing relationship between the plurality of valid data, each set of selection control signals is composed of a data selection signal, a clock selection signal, and a enable selection signal, and a plurality of selector signals respectively as