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CN-121979373-A - Optimization method of computing power memory card and computing power memory card

CN121979373ACN 121979373 ACN121979373 ACN 121979373ACN-121979373-A

Abstract

The application is suitable for the technical field of a calculation force memory card, and provides an optimization method of the calculation force memory card and the calculation force memory card. The method comprises the steps of adjusting a feedback resistor network of a first power supply chip, improving output voltage of the first power supply chip from first default voltage to first target voltage, adjusting a capacitance value of a time sequence capacitor connected with an enabling end or an output end of the first power supply chip to adjust power-on time sequence of the first power supply chip, adjusting a feedback resistor network of a second power supply chip, improving output voltage of the second power supply chip from second default voltage to second target voltage, and replacing an output inductor of the second power supply chip with a replacement inductor with higher power. According to the embodiment of the application, through the collaborative optimization of voltage lifting, time sequence matching and load capacity enhancement, the power memory card can be normally initialized and stably operated under various power supply voltage platforms, and the yield of the power memory card is obviously improved.

Inventors

  • LI CHULONG
  • DENG WEI

Assignees

  • 深圳市钜邦科技有限公司

Dates

Publication Date
20260505
Application Date
20260407

Claims (12)

  1. 1. A method of optimizing a computing power memory card, comprising: Adjusting a feedback resistance network of a first power supply chip, and increasing the output voltage of the first power supply chip from a first default voltage to a first target voltage, wherein the first power supply chip is used for providing a flash memory input/output interface power supply; Adjusting the capacitance value of a time sequence capacitor connected with an enabling end or an output end of the first power supply chip to adjust the power-on time sequence of the first power supply chip; adjusting a feedback resistance network of a second power supply chip, and increasing the output voltage of the second power supply chip from a second default voltage to a second target voltage, wherein the second power supply chip is used for providing a flash memory core power supply; replacing the output inductor of the second power supply chip with a replacement inductor with higher power; the power-saving memory card can be normally initialized and stably operated under various power supply voltage platforms by adjusting the feedback resistor network, adjusting the capacitance value of the time sequence capacitor, replacing the output inductor and improving the output voltage of the second power supply chip, so that defective products are optimized to be good products.
  2. 2. The method of claim 1, wherein the first default voltage comprises 1.2V and 1.8V, and the first default voltage and the first target voltage are raised in a range of 3% to 5%.
  3. 3. The method of optimizing a computing power memory card of claim 1, wherein adjusting the feedback resistance network of the first power chip comprises: And replacing a first resistor in the feedback resistor network with a resistor with a first resistance value, or replacing a second resistor in the feedback resistor network with a resistor with a second resistance value, or replacing the first resistor and the second resistor simultaneously.
  4. 4. The method of optimizing a computing power memory card of claim 1, wherein adjusting the capacitance value of the time-series capacitor comprises: And replacing the time sequence capacitor with a capacitance smaller than that of the original capacitor so as to delay the power-on time of the first power supply chip.
  5. 5. The method of optimizing a power storage card of claim 1, wherein the second default voltage is 3.3V, and the second default voltage and the second target voltage are raised by 3% to 10% in a 3.3V range.
  6. 6. The method of optimizing a computing power memory card of claim 1, further comprising: And replacing the power management chip of the second power supply chip with a power management chip matched with the replacement inductor.
  7. 7. The method of claim 1, wherein the plurality of power supply voltage platforms includes a first platform and a second platform having different power supply voltages, the power supply voltage of the first platform being lower than the power supply voltage of the second platform.
  8. 8. A computing power memory card, comprising: The first power supply chip is used for providing a flash memory input/output interface power supply, the feedback resistor network is configured to increase the output voltage of the flash memory input/output interface power supply from a first default voltage to a first target voltage, and the time sequence capacitor connected with the enabling end or the output end of the feedback resistor network is configured to have an adjusted capacitance value so as to adjust the power-on time sequence of the flash memory input/output interface power supply; and the second power supply chip is used for providing a flash memory core power supply, the feedback resistor network is configured to increase the output voltage of the flash memory core power supply from a second default voltage to a second target voltage, and the output inductor is configured as an alternate inductor after power increase.
  9. 9. The computing power memory card of claim 8, wherein the first default voltage comprises 1.2V and 1.8V, and the first default voltage and the first target voltage are elevated in a range of 3% to 5%.
  10. 10. The computing power memory card of claim 8, wherein the timing capacitor has a capacitance greater than the capacitance of the original capacitor to delay the power-up time of the first power chip.
  11. 11. The computing power memory card of claim 8, wherein the second default voltage is 3.3V, and the second default voltage and the second target voltage are raised by 3% to 10% over a 3.3V range.
  12. 12. The computing power memory card of claim 8, wherein the power management chip of the second power chip is a power management chip that matches the replacement inductance.

Description

Optimization method of computing power memory card and computing power memory card Technical Field The invention relates to the technical field of a computing power memory card, in particular to an optimization method of the computing power memory card and the computing power memory card. Background With the popularity of AI applications, a memory card (such as a memory card, a flash memory card, etc.) needs to be deployed with local computing power, and typically includes a plurality of power supply chips therein for providing working voltages to a flash memory input/output interface and a flash memory core, respectively. In the actual production process, the yield of the power storage card is affected by various factors, and especially when the power storage card is used on different power supply voltage platforms (such as different types of mainboards and different brands of hosts), the problem that the yield does not reach the standard often occurs. According to analysis, the existing power storage card is usually optimized for a certain typical voltage platform in design, and when the power storage card is applied to a platform with lower power supply voltage or larger voltage fluctuation, the power storage card has the adverse phenomena of initialization failure (namely 'disc falling' phenomenon), formatting blocking and the like. The above problems result in that a part of the power storage card cannot work normally under a specific platform, and is judged to be defective, resulting in large production loss. Disclosure of Invention The invention provides an optimization method of a power calculation memory card and the power calculation memory card, which are used for solving the technical problem that the yield of the existing power calculation memory card is low under different power supply voltage platforms. In a first aspect, an embodiment of the present application provides a method for optimizing a computing power memory card, including: Adjusting a feedback resistance network of a first power supply chip, and increasing the output voltage of the first power supply chip from a first default voltage to a first target voltage, wherein the first power supply chip is used for providing a flash memory input/output interface power supply; Adjusting the capacitance value of a time sequence capacitor connected with an enabling end or an output end of the first power supply chip to adjust the power-on time sequence of the first power supply chip; adjusting a feedback resistance network of a second power supply chip, and increasing the output voltage of the second power supply chip from a second default voltage to a second target voltage, wherein the second power supply chip is used for providing a flash memory core power supply; replacing the output inductor of the second power supply chip with a replacement inductor with higher power; the power-saving memory card can be normally initialized and stably operated under various power supply voltage platforms by adjusting the feedback resistor network, adjusting the capacitance value of the time sequence capacitor, replacing the output inductor and improving the output voltage of the second power supply chip, so that defective products are optimized to be good products. In a second aspect, an embodiment of the present application provides an optimizing apparatus for a computing power memory card, including: The first voltage adjusting module is used for adjusting a feedback resistor network of a first power supply chip, and improving the output voltage of the first power supply chip from a first default voltage to a first target voltage, wherein the first power supply chip is used for providing a flash memory input/output interface power supply; the time sequence adjusting module is used for adjusting the capacitance value of a time sequence capacitor connected with the enabling end or the output end of the first power supply chip so as to adjust the power-on time sequence of the first power supply chip; the second voltage adjusting module is used for adjusting a feedback resistor network of a second power supply chip, and improving the output voltage of the second power supply chip from a second default voltage to a second target voltage, wherein the second power supply chip is used for providing a flash memory core power supply; And the inductor replacement module is used for replacing the output inductor of the second power supply chip with a replacement inductor with higher power. The embodiment of the application provides an optimization method of a power calculation memory card, which comprises the steps of adjusting a feedback resistor network of a first power supply chip, improving the output voltage of the first power supply chip from a first default voltage to a first target voltage, wherein the first power supply chip is used for providing a flash memory input/output interface power supply, adjusting the capacitance value of a time sequence capac