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CN-121979479-A - FIFO circuit and electronic device

CN121979479ACN 121979479 ACN121979479 ACN 121979479ACN-121979479-A

Abstract

The application provides a FIFO circuit and electronic equipment, and relates to the technical field of circuit design. The first address management module is used for determining the virtual FIFO meeting the first hit condition in the n virtual FIFOs as a first virtual FIFO in each clock period, generating a write address corresponding to a write pointer of the first virtual FIFO in the memory, sending the write address to the memory controller, controlling the first input register corresponding to the first virtual FIFO to output the target data to the memory controller, and writing the target data to the memory based on the write address. The application can effectively reduce the duty area of the whole circuit of a plurality of FIFOs and improve the whole area efficiency.

Inventors

  • Request for anonymity
  • Request for anonymity

Assignees

  • 摩尔线程智能科技(北京)股份有限公司

Dates

Publication Date
20260505
Application Date
20251212

Claims (14)

  1. 1. The FIFO circuit is characterized by comprising an input buffer memory module, a storage module and a first address management module; The input buffer module comprises n input registers, is used for receiving n target data to be stored, which are output by an upstream circuit, and respectively writes the n target data into the n input registers; The storage module comprises a storage controller and a memory, wherein the memory is divided into n virtual FIFOs, and the n virtual FIFOs are in one-to-one correspondence with the n input registers; The first address management module is connected with the input buffer module and the storage controller, and is used for managing a write pointer of each virtual FIFO, determining a virtual FIFO meeting a first hit condition in the n virtual FIFOs as a first virtual FIFO in each clock period, generating a write address corresponding to the write pointer of the first virtual FIFO in the memory, sending the write address to the storage controller, and controlling a first input register to output the target data to the storage controller, wherein the meeting of the first hit condition comprises that the storage is not full and the target data which is not written into the virtual FIFO is stored in the corresponding input register, and the first input register is the input register corresponding to the first virtual FIFO; the memory controller is configured to write the target data to the memory based on the write address.
  2. 2. The FIFO circuit as claimed in claim 1, wherein the FIFO circuit has a one-to-one correspondence with the input register for the target data to be stored each time received from the upstream circuit; The state confirmation module is connected with the n input registers and is used for determining that the target data currently stored in the n input registers are written into the invalid register of the virtual FIFO under the condition that the n target data to be stored output by the upstream circuit are received, writing the corresponding target data into the invalid register until the n input registers are written into the corresponding target data, and sending a completion signal to the upstream circuit.
  3. 3. The FIFO circuit according to claim 2, wherein the FIFO circuit receives a valid signal corresponding to the target data output by the upstream circuit while receiving the target data to be stored output by the upstream circuit; The state confirmation module is further used for outputting valid signals of the corresponding target data to the n input registers under the condition that n target data to be stored, which are output by an upstream circuit, are received; the state confirmation module is further configured to output an invalidation signal of the target data to the invalidation register after writing the corresponding target data to the invalidation register, and output a completion signal to the upstream circuit in a case where the invalidation signal is output to all the input registers.
  4. 4. A FIFO circuit as claimed in claim 2 or 3, wherein, The first address management module is connected with the state confirmation module and is used for outputting the identifier of the first virtual FIFO to the state confirmation module after controlling a first input register to output the target data to the storage controller; The state confirmation module is further configured to record the first input register as the invalid register if the identifier of the first virtual FIFO is received, and the meeting the first hit condition includes that the storage is not full and the corresponding input register is not recorded as the invalid register.
  5. 5. The FIFO circuit as claimed in claim 1, wherein the input buffer module further comprises a first selection module; the first address management module is further configured to output, to the first selection module, an identification of a first virtual FIFO after determining, as the first virtual FIFO, a virtual FIFO that satisfies a first hit condition of the n virtual FIFOs; The first selection module is connected with the n input registers and the storage controller, and is used for reading the target data in the first input register and outputting the target data to the storage controller under the condition that the identification of the first virtual FIFO is received.
  6. 6. The FIFO circuit as claimed in claim 1, wherein the first address management module comprises a pointer management sub-module, a first poll arbiter, and a first compute sub-module; the pointer management submodule is connected with the storage controller and is used for managing the write pointer of each virtual FIFO; The first polling arbiter is connected with the first computing submodule and the input buffer module, and is used for determining a virtual FIFO meeting a first hit condition in the n virtual FIFOs as a first virtual FIFO in each clock period, and outputting the identification of the first virtual FIFO to the first computing submodule; The first computing sub-module is connected with the pointer management sub-module and the storage controller and is used for generating a write address corresponding to a write pointer of the first virtual FIFO in the memory and sending the write address to the storage controller; The first poll arbiter is further for controlling the first input register to output the target data to the memory controller.
  7. 7. The FIFO circuit of claim 1, wherein the memory is divided into n virtual FIFOs in the row direction; The first address management module is further configured to determine, in each clock cycle, one of the n virtual FIFOs satisfying a first hit condition as the first virtual FIFO, and generate, according to a write pointer of the first virtual FIFO and a first address of the first virtual FIFO, a write address corresponding to the write pointer of the first virtual FIFO in the memory.
  8. 8. The FIFO circuit of any one of claims 1 to 7, further comprising an output buffer module and a second address management module; the output buffer module comprises n output registers which are in one-to-one correspondence with the virtual FIFOs, and the output registers are used for reading data by a downstream circuit; the first address management module is further configured to manage a read pointer of each virtual FIFO; The second address management module is connected with the first address management module, the output buffer module and the storage controller and is used for determining a virtual FIFO meeting a second hit condition in the n virtual FIFOs as a second virtual FIFO in each clock period, generating a corresponding read address of a read pointer of the second virtual FIFO in the memory and sending the read address to the storage controller, wherein the meeting the second hit condition comprises that data indicated by the read pointer are not read and corresponding target data currently stored by the output register are read by a downstream circuit; the storage controller is used for outputting target data indicated by the read address to the output buffer module based on the read address; The second address management module is further configured to control a first output register to write demand data, where the first output register is an output register corresponding to the second virtual FIFO, and the demand data is target data stored in the second virtual FIFO among target data indicated by the read address.
  9. 9. The FIFO circuit as claimed in claim 8, wherein the output buffer module comprises a second selection module; The second address management module is further configured to output, to the second selection module, an identification of a second virtual FIFO after determining, as the second virtual FIFO, a virtual FIFO that satisfies a second hit condition of the n virtual FIFOs; The second selection module is connected with the n output registers and the storage controller and is used for writing the demand data into the first output register under the condition that the identification of the second virtual FIFO is received.
  10. 10. The FIFO circuit as claimed in claim 8, wherein the output buffer module comprises a third selection module; The third selection module is connected with the n output registers and is used for receiving the register identification output by the downstream circuit, reading the target data currently stored in the output register indicated by the register identification and outputting the read target data to the downstream circuit.
  11. 11. The FIFO circuit as claimed in any one of claims 8 to 10, wherein the output buffer module further comprises a status flag module; The state marking module is used for receiving the register identification output by the downstream circuit, recording the output register indicated by the register identification as an invalid register, wherein the step of meeting the second hit condition comprises that the data indicated by the read pointer are not read, and the corresponding output register is recorded as the invalid register.
  12. 12. The FIFO circuit as claimed in claim 8, wherein the second address management module comprises a second poll arbiter and a second calculation sub-module; The second polling arbiter is connected with the second calculation submodule and the output buffer module, and is used for determining a virtual FIFO meeting a second hit condition in the n virtual FIFOs as a second virtual FIFO in each clock period, and outputting the identification of the second virtual FIFO to the second calculation submodule; The second computing sub-module is connected with the first address management module and the storage controller and is used for generating a read address corresponding to the read pointer of the second virtual FIFO in the memory and sending the read address to the storage controller; the second polling arbiter is further configured to control the output register corresponding to the second virtual FIFO to write the demand data.
  13. 13. The FIFO circuit of claim 8, wherein the memory is divided into n virtual FIFOs in the row direction; The second address management module is further configured to determine, in each clock cycle, one of the n virtual FIFOs satisfying a second hit condition as the second virtual FIFO, and generate, according to a read pointer of the second virtual FIFO and a first address of the second virtual FIFO, a read address corresponding to the read pointer of the second virtual FIFO in the memory.
  14. 14. An electronic device comprising the FIFO circuit of any of claims 1 to 13.

Description

FIFO circuit and electronic device Technical Field The present application relates to the field of circuit technologies, and in particular, to a FIFO circuit and an electronic device. Background The first-in first-out queue (First Input First Output, FIFO) is a linear data structure that follows the first-in first-out principle, with the core rule being that the earliest data into the queue is output first. Multiple FIFOs are currently commonly employed to effect buffering and transfer of data. In particular, the upstream circuit may write multiple data to different FIFOs, respectively, in a single clock cycle, such that each FIFO may receive one data in that clock cycle for downstream circuit reading. However, because each FIFO requires separate wiring and peripheral circuitry, the footprint of the overall circuitry of the multiple FIFOs is typically large, resulting in overall area inefficiency. Disclosure of Invention In view of the foregoing, embodiments of the present application have been made to provide a FIFO circuit and an electronic device that overcome or at least partially solve the foregoing problems, so as to solve the problem that the overall circuit of the target multiple FIFOs has a larger duty area and a lower overall area efficiency. In order to solve the above problems, in a first aspect, there is provided a FIFO circuit comprising an input buffer module, a storage module, and a first address management module; The input buffer module comprises n input registers, is used for receiving n target data to be stored, which are output by an upstream circuit, and respectively writes the n target data into the n input registers; The storage module comprises a storage controller and a memory, wherein the memory is divided into n virtual FIFOs, and the n virtual FIFOs are in one-to-one correspondence with the n input registers; The first address management module is connected with the input buffer module and the storage controller, and is used for managing a write pointer of each virtual FIFO, determining a virtual FIFO meeting a first hit condition in the n virtual FIFOs as a first virtual FIFO in each clock period, generating a write address corresponding to the write pointer of the first virtual FIFO in the memory, sending the write address to the storage controller, and controlling a first input register to output the target data to the storage controller, wherein the meeting of the first hit condition comprises that the storage is not full and the target data which is not written into the virtual FIFO is stored in the corresponding input register, and the first input register is the input register corresponding to the first virtual FIFO; the memory controller is configured to write the target data to the memory based on the write address. Optionally, the FIFO circuit has a one-to-one correspondence with the input registers for each time the target data to be stored received from the upstream circuit; The state confirmation module is connected with the n input registers and is used for determining that the target data currently stored in the n input registers are written into the invalid register of the virtual FIFO under the condition that the n target data to be stored output by the upstream circuit are received, writing the corresponding target data into the invalid register until the n input registers are written into the corresponding target data, and sending a completion signal to the upstream circuit. Optionally, the FIFO circuit receives the valid signal corresponding to the target data output by the upstream circuit while receiving the target data to be stored output by the upstream circuit; The state confirmation module is further used for outputting valid signals of the corresponding target data to the n input registers under the condition that n target data to be stored, which are output by an upstream circuit, are received; the state confirmation module is further configured to output an invalidation signal of the target data to the invalidation register after writing the corresponding target data to the invalidation register, and output a completion signal to the upstream circuit in a case where the invalidation signal is output to all the input registers. Optionally, the first address management module is connected to the state confirmation module, and is configured to output, after controlling a first input register to output the target data to the storage controller, an identifier of the first virtual FIFO to the state confirmation module; The state confirmation module is further configured to record the first input register as the invalid register if the identifier of the first virtual FIFO is received, and the meeting the first hit condition includes that the storage is not full and the corresponding input register is not recorded as the invalid register. Optionally, the input buffer module further comprises a first selection module; the first address management module is fu