Search

CN-121979481-A - Zero arithmetic overhead address generation method and circuit based on bit extraction

CN121979481ACN 121979481 ACN121979481 ACN 121979481ACN-121979481-A

Abstract

The invention discloses a zero arithmetic overhead address generation method and a circuit based on bit extraction, wherein the method comprises the steps of detecting the most significant bit position of an input fixed point integer to determine an interval index; and splicing the interval index and the offset index bit to generate a storage address. The circuit comprises a most significant bit detection module, a bit extraction module and an address splicing module. The invention converts the existing division operation into simple bit extraction operation by utilizing the mathematical characteristic of the division of the power interval of 2, and completely eliminates the arithmetic operation in the address generation process. Only the priority encoder, multiplexer and bit concatenation logic are required, without any adders, multipliers or dividers. The implementation result on the FPGA shows that the circuit only consumes 5-7 LUTs, is reduced by more than 90% compared with the existing method, and is particularly suitable for processing application of an embedded system with limited resources and high throughput rate data flow.

Inventors

  • ZHANG JIN
  • LIU FEI
  • CHEN ZIMING
  • LI ZHONGYANG

Assignees

  • 金陵科技学院

Dates

Publication Date
20260505
Application Date
20260202

Claims (10)

  1. 1. The zero arithmetic overhead address generation method based on bit extraction is characterized by comprising the following steps: s1, determining interval indexes: Fixed point integer for input Detecting the position of the most significant bit in its binary representation The position is directly processed by the preset priority coding logic Mapping to interval index ; S2, bit extraction operation: According to interval index From fixed point integers by bit extraction operations In-range offset index is directly extracted : ; Wherein the method comprises the steps of In order to input the decimal place width, As the reference index(s), Is the index bit width; S3, address splicing: Indexing intervals Offset index from intra-interval Performing bit concatenation to generate a final storage address: 。
  2. 2. The method for generating a zero arithmetic overhead address based on bit extraction according to claim 1, wherein in step S1, fixed-point integers The most significant bit detection of (2) adopts priority coding logic, and is specifically as follows: If it is Then ; If it is Then ; And so on until the interval index is determined 。
  3. 3. The method of generating a zero arithmetic overhead address based on bit extraction according to claim 1, wherein in step S1, when the input is a floating point number, the fixed point integer The mantissa portion corresponding to the floating point number.
  4. 4. The method for generating a zero arithmetic overhead address based on bit extraction according to claim 1, wherein in step S2, the bit extraction operation is implemented in hardware by a multiplexer, and the bit extraction operation is specifically as follows: ; Wherein the method comprises the steps of Is the first The lower bound of the individual intervals is defined, For the width of the section to be the same, Is the number of sampling points.
  5. 5. The method of generating a zero arithmetic overhead address based on bit extraction according to claim 1, wherein in step S2, indexes are indexed for different intervals Extracting fixed point integers Is specified as follows: When (when) At the time of extraction of ; When (when) At the time of extraction of ; When (when) At the time of extraction of 。
  6. 6. A zero arithmetic overhead address generation circuit based on bit extraction, comprising: The most significant bit detection module: Employing a priority encoder structure for detecting fixed point integers Most significant bit positions of (2) And outputs the interval index ; And a bit extraction module: Adopting a multiplexer structure for indexing according to the interval From fixed point integers Selecting and extracting the corresponding Bit data as intra-interval offset index ; An address splicing module: For indexing intervals Offset index from intra-interval Performing bit concatenation to generate a storage address 。
  7. 7. The zero arithmetic overhead address generation circuit of claim 6, further comprising a primary address pipeline register coupled to an output of the address splicing module, the primary address pipeline register for latching the generated memory address at a clock edge The address generation combinational logic is isolated from subsequent memory read paths, ensuring that address generation and lookup operations are performed in different clock cycles.
  8. 8. The zero arithmetic overhead address generation circuit of claim 6, wherein the most significant bit detection module comprises bit detection units that respectively detect fixed point integers Is the first of (2) Bit to the first Bits, and according to the priority coding logic, section indexes are determined by priority according to the output of the bit detection unit 。
  9. 9. The zero arithmetic overhead address generation circuit based on bit extraction of claim 6, wherein the bit extraction module comprises Bit segment extraction channels and a multiplexer, each bit segment extraction channel corresponding to a section index value for extracting fixed-point integers Corresponding to (a) Bit data, the multiplexer is 1-Selecting multiplexer according to interval index Selecting the output of the corresponding channel as the intra-interval offset index 。
  10. 10. The zero arithmetic overhead address generation circuit based on bit extraction of claim 6, wherein the address stitching module is to Interval index of bits Is placed in a high position, and is positioned in the high position, Intra-interval offset index of bits Placed at a low position to form Memory address of bits 。

Description

Zero arithmetic overhead address generation method and circuit based on bit extraction Technical Field The invention relates to the technical field of digital circuit design and FPGA hardware implementation, in particular to a zero arithmetic overhead address generation method and circuit based on bit extraction for lookup table addressing, which are particularly suitable for piecewise approximation calculation of cube root, square root, logarithm and other nonlinear functions. Background Look-Up tables (LUTs) are commonly used function approximation techniques in digital signal processing and hardware acceleration to implement fast approximate computation of complex functions by pre-computing the function values and storing them in memory. In a lookup table-based function approximation system, address generation is a key link, and the efficiency of the address generation directly influences the overall performance and resource consumption of the system. Conventional look-up table address generation methods typically require input normalization and index calculation. Taking a nonlinear function such as a cube root as an example, in order to efficiently use a storage space, an input domain is generally divided into a plurality of subintervals, and an independent lookup table is built for each subinterval. At run-time, it is necessary to first determine the subinterval to which the input belongs and then calculate the relative position of the input within that interval as a look-up table index. The existing address generation method mainly faces the following technical problems: (1) The cost of division operation is that in the traditional method, division operation is needed to calculate the offset index in the interval. Let y be the input, lr be the interval lower bound, wr be the interval width, and N be the sampling point number, the offset index idx=floor ((y-Lr)/wr×n). Division operations require a large amount of logic resources or dedicated dividers to be consumed in hardware implementations, significantly increasing system complexity and delay. (2) Multiplication overhead-even if shifting is used to replace part of the operation, the normalized index map may still require multiplication, consuming DSP resources or a large amount of LUT resources. (3) The interval detection complexity is that the existing method generally adopts comparator cascade or binary search to determine the interval to which the input belongs, and as the number of intervals increases, the logic complexity and delay correspondingly increase. (4) Pipeline efficiency the introduction of arithmetic operations increases the critical path length, limiting the highest operating frequency and pipeline efficiency of the system. Therefore, a method for implementing address generation by simple logic operation without arithmetic operation is needed to meet the requirement of low latency and low resource consumption of the resource-constrained embedded system. Disclosure of Invention Aiming at the problems of high resource consumption and large delay caused by the fact that the existing lookup table address generation method needs arithmetic operations such as division, multiplication and the like, the invention provides a zero arithmetic overhead address generation method and a zero arithmetic overhead address generation circuit based on bit extraction. In order to achieve the above purpose, the technical scheme adopted by the invention is as follows: The zero arithmetic overhead address generation method based on bit extraction comprises the following steps: s1, determining interval indexes: Fixed point integer for input Detecting the position of the most significant bit in its binary representationThe position is directly processed by the preset priority coding logicMapping to interval index; S2, bit extraction operation: According to interval index From fixed point integers by bit extraction operationsIn-range offset index is directly extracted: ; Wherein the method comprises the steps ofIn order to input the decimal place width,As the reference index(s),Is the index bit width; S3, address splicing: Indexing intervals Offset index from intra-intervalPerforming bit concatenation to generate a final storage address:。 as a preferable technical scheme of the invention, in the step S1, fixed-point integers are adopted The most significant bit detection of (2) adopts priority coding logic, and is specifically as follows: If it is Then; If it isThen; And so on until the interval index is determined。 As a preferable technical scheme of the invention, in step S1, when the input is a floating point number, the fixed point integerThe mantissa portion corresponding to the floating point number. In step S2, the bit extraction operation is implemented in hardware through a multiplexer, and the bit extraction operation is specifically as follows: ; Wherein the method comprises the steps of Is the firstThe lower bound of the individual intervals is de