Search

CN-121979485-A - 5-Bit adder, arithmetic operation circuit, calculation chip, and electronic device

CN121979485ACN 121979485 ACN121979485 ACN 121979485ACN-121979485-A

Abstract

The invention relates to the technical field of adder circuits, in particular to a 5-bit adder, an arithmetic operation circuit, a computing chip and electronic equipment, wherein the adder is composed of 40 transistors and comprises a plurality of exclusive-OR gates and inverters, a first input node of a third exclusive-OR gate is a first data input node, a second input node of the third exclusive-OR gate is a second data input node, an output node of the second inverter is a third data input node, a first input node of the first exclusive-OR gate is a fourth data input node, a second input node of the first exclusive-OR gate is a fifth data input node, an output node of the first inverter is a data output node, an output node of the third inverter is a first carry signal node, and an output node of the fifth inverter is a second carry signal node. To solve the problem of the related art that the 5-bit adder with high energy efficiency, small area and high operation speed is lacking.

Inventors

  • ZHANG QIRONG
  • ZHU SHENGLAN

Assignees

  • 苏州宽温电子科技有限公司

Dates

Publication Date
20260505
Application Date
20260409

Claims (10)

  1. 1. The 5-bit adder is characterized by comprising a first exclusive-OR gate, a second exclusive-OR gate, a third exclusive-OR gate, a first inverter, a second inverter, a third inverter, a fourth inverter, a fifth inverter, a first PMOS tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a fifth PMOS tube, a sixth PMOS tube, a first NMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube and a sixth NMOS tube; the first exclusive-OR gate, the second exclusive-OR gate and the third exclusive-OR gate have the same internal structure and each comprise 6 MOS tubes; The first inverter, the second inverter, the third inverter, the fourth inverter and the fifth inverter have the same internal structure and comprise 2 MOS tubes; the output node of the first exclusive-or gate is connected with the first input node of the second exclusive-or gate; The output node of the second exclusive-or gate is connected with the input node of the first inverter; The output node of the third exclusive-or gate is connected with the grid electrode of the first PMOS tube, the grid electrode of the first NMOS tube, the source electrode of the second PMOS tube and the source electrode of the second NMOS tube; The source electrode of the first PMOS tube is connected with the output node of the second inverter and the grid electrode of the second PMOS tube, and the drain electrode of the first PMOS tube is connected with the drain electrode of the first NMOS tube, the drain electrode of the second PMOS tube, the drain electrode of the second NMOS tube, the source electrode of the third PMOS tube, the source electrode of the third NMOS tube and the second input node of the second exclusive-OR gate; The source electrode of the second NMOS tube is connected with the input node of the second inverter, the source electrode of the fifth PMOS tube and the source electrode of the fifth NMOS tube; The grid electrode of the third PMOS tube is connected with the grid electrode of the fourth NMOS tube and is controlled by the first input node of the second exclusive-OR gate, and the drain electrode of the third PMOS tube is connected with the drain electrode of the third NMOS tube, the drain electrode of the fourth PMOS tube, the drain electrode of the fourth NMOS tube and the input node of the third inverter; The grid electrode of the third NMOS tube is connected with the grid electrode of the fourth PMOS tube and the first output node of the second exclusive-OR gate; the source electrode of the fourth PMOS tube is connected with the source electrode of the fourth NMOS tube and is controlled by the first input node of the first exclusive-OR gate; The grid electrode of the fifth PMOS tube is connected with the grid electrode of the sixth NMOS tube and the output node of the fourth inverter, and the drain electrode of the fifth PMOS tube is connected with the drain electrode of the fifth NMOS tube, the drain electrode of the sixth PMOS tube, the drain electrode of the sixth NMOS tube and the input node of the fifth inverter; The grid electrode of the fifth NMOS tube is connected with the grid electrode of the sixth PMOS tube, the output node of the third exclusive-OR gate and the input node of the fourth inverter; the source electrode of the sixth PMOS tube is connected with the source electrode of the sixth NMOS tube and is controlled by the first input node of the third exclusive-OR gate; The first input node of the third exclusive-or gate is a first data input node of the 5-bit adder, the second input node of the third exclusive-or gate is a second data input node of the 5-bit adder, the output node of the second inverter is a third data input node of the 5-bit adder, the first input node of the first exclusive-or gate is a fourth data input node of the 5-bit adder, the second input node of the first exclusive-or gate is a fifth data input node of the 5-bit adder, the output node of the first inverter is a data output node of the 5-bit adder, the output node of the third inverter is a first carry signal node of the 5-bit adder, and the output node of the fifth inverter is a second carry signal node of the 5-bit adder.
  2. 2. The 5-bit adder according to claim 1, wherein said second exclusive-or gate comprises a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, and a ninth NMOS transistor; the source electrode of the seventh PMOS tube is connected with a power supply; The grid electrode of the seventh PMOS tube is connected with the output node of the first exclusive-OR gate, the grid electrode of the seventh NMOS tube, the source electrode of the eighth PMOS tube, the grid electrode of the ninth PMOS tube and the grid electrode of the third NMOS tube; The drain electrode of the seventh PMOS tube is connected with the drain electrode of the seventh NMOS tube, the source electrode of the eighth NMOS tube, the grid electrode of the ninth NMOS tube and the grid electrode of the third PMOS tube, and is used for controlling the grid electrode of the third PMOS tube and the grid electrode of the fourth NMOS tube based on the first input node of the second exclusive-OR gate; the source electrode of the seventh NMOS tube is grounded; The grid electrode of the eighth PMOS tube is connected with the grid electrode of the eighth NMOS tube, the source electrode of the ninth PMOS tube, the source electrode of the ninth NMOS tube and the drain electrode of the first PMOS tube; The drain electrode of the eighth PMOS tube is connected with the drain electrode of the eighth NMOS tube, the drain electrode of the ninth PMOS tube and the drain electrode of the ninth NMOS tube; The connection node between the gate of the seventh PMOS transistor and the gate of the seventh NMOS transistor is a first input node of the second exclusive-or gate, the connection node between the gate of the eighth PMOS transistor and the gate of the eighth NMOS transistor is a second input node of the second exclusive-or gate, and the connection node between the drain of the ninth PMOS transistor and the drain of the ninth NMOS transistor is an output node of the second exclusive-or gate.
  3. 3. The 5-bit adder according to claim 2, wherein said second exclusive-or gate is configured to: Under the condition that a first input node of the second exclusive-OR gate is set to be 1 and a second input node of the second exclusive-OR gate is set to be 0, an output node of the second exclusive-OR gate is set to be 1; under the condition that a first input node of the second exclusive-OR gate is set to 0 and a second input node of the second exclusive-OR gate is set to 1, an output node of the second exclusive-OR gate is set to 1; under the condition that a first input node of the second exclusive-OR gate is set to 1 and a second input node of the second exclusive-OR gate is set to 1, an output node of the second exclusive-OR gate is 0; and under the condition that the first input node of the second exclusive-OR gate is set to 0 and the second input node of the second exclusive-OR gate is set to 0, the output node of the second exclusive-OR gate is set to 0.
  4. 4. The 5-bit adder according to claim 1, wherein said first inverter comprises a tenth PMOS transistor and a tenth NMOS transistor; The source electrode of the tenth PMOS tube is connected with a power supply, the grid electrode of the tenth PMOS tube is connected with the grid electrode of the tenth NMOS tube and the output node of the second exclusive-OR gate, and the drain electrode of the tenth PMOS tube is connected with the drain electrode of the tenth NMOS tube; the source electrode of the tenth NMOS tube is grounded; the connection node between the gate of the tenth PMOS transistor and the gate of the tenth NMOS transistor is an input node of the first inverter, and the connection node between the drain of the tenth PMOS transistor and the drain of the tenth NMOS transistor is an output node of the first inverter.
  5. 5. The 5-bit adder according to claim 1, wherein said third exclusive-or gate comprises an eleventh PMOS transistor and an eleventh NMOS transistor, said first exclusive-or gate comprises a twelfth PMOS transistor and a twelfth NMOS transistor; The source electrode of the eleventh PMOS tube is connected with a power supply, and the grid electrode of the eleventh PMOS tube is connected with the grid electrode of the eleventh NMOS tube; the drain electrode of the eleventh PMOS tube is connected with the drain electrode of the eleventh NMOS tube and the source electrode of the sixth PMOS tube, and is used for controlling the source electrode of the sixth PMOS tube and the source electrode of the sixth NMOS tube based on the first input node of the third exclusive-OR gate; the source electrode of the eleventh NMOS tube is grounded; the source electrode of the twelfth PMOS tube is connected with a power supply, and the grid electrode of the twelfth PMOS tube is connected with the grid electrode of the twelfth NMOS tube; The drain electrode of the twelfth PMOS tube is connected with the drain electrode of the twelfth NMOS tube and the source electrode of the fourth PMOS tube, and is used for controlling the source electrode of the fourth PMOS tube and the source electrode of the fourth NMOS tube based on the first input node of the first exclusive-OR gate; the source electrode of the twelfth NMOS tube is grounded; The connection node between the gate of the eleventh PMOS transistor and the gate of the eleventh NMOS transistor is a first input node of the third xor gate, and the connection node between the gate of the twelfth PMOS transistor and the gate of the twelfth NMOS transistor is a first input node of the first xor gate.
  6. 6. The 5-bit adder according to claim 1, wherein the logical relation among the data output node, the first carry signal node, and the second carry signal node of said 5-bit adder is: ; ; ; In the formula, Which represents the data output node of the data processing device, Representing the output node of the first exclusive or gate, Representing an exclusive nor operation is performed on the data, Representing the connection node of the drain electrode of the second PMOS tube and the drain electrode of the second NMOS tube, A fourth data input node is represented which, Representing an exclusive-or operation, A fifth data input node is represented and, A first data input node is represented and, Representing a second data input node and, Representing the input node of the second inverter, A first carry signal node is represented and, Representing the output node of the third exclusive or gate, A third data input node is represented and, Representing a second carry signal node.
  7. 7. An arithmetic operation circuit, characterized in that the arithmetic operation circuit is provided with the 5-bit adder according to any one of claims 1 to 6.
  8. 8. A computing chip, characterized in that the computing chip is provided with the arithmetic operation circuit of claim 7.
  9. 9. The computing chip of claim 8, wherein the computing chip is a memory integrated chip or a CPU chip or a GPU chip.
  10. 10. An electronic device, characterized in that it is provided with a computing chip as claimed in any one of claims 8 to 9.

Description

5-Bit adder, arithmetic operation circuit, calculation chip, and electronic device Technical Field The invention relates to the technical field of adder circuits, in particular to a 5-bit adder, an arithmetic operation circuit, a computing chip and electronic equipment. Background The adder is a basic operation module which is integrated with memory and is widely used by various calculation chips such as CPU, GPU and the like, and is a basic element of an operation unit such as a multiplier, a floating point arithmetic unit and the like. In other words, the adder has high application frequency in the computing chip, and occupies a larger hardware area of the chip. Therefore, the hardware area, power consumption and operation delay index of the adder directly influence the performance of the chip. In the related art, a 28T carry full adder cascade mode is adopted to carry out 5-bit (5 bit) addition operation, the number of the full adder transistors is large, the hardware area cost is large, the signal propagation path is long, the MOS transistor turnover times are large, and when the circuit power consumption is higher, larger operation delay is generated, so that the development requirements of the current calculation chip on high energy efficiency, small area and high operation speed are difficult to meet. Aiming at the problem of lack of a 5-bit adder with high energy efficiency, small area and high operation speed in the related technology, no effective solution is proposed at present. Disclosure of Invention The invention provides a 5-bit adder, an arithmetic operation circuit, a computing chip and electronic equipment, which at least solve the problem that the 5-bit adder with high energy efficiency, small area and high operation speed is lacked in the related technology. The invention provides a 5-bit adder, which comprises a first exclusive-OR gate, a second exclusive-OR gate, a third exclusive-OR gate, a first inverter, a second inverter, a third inverter, a fourth inverter, a fifth inverter, a first PMOS tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a fifth PMOS tube, a sixth PMOS tube, a first NMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube and a sixth NMOS tube, wherein the internal structures of the first exclusive-OR gate, the second exclusive-OR gate and the third exclusive-OR gate are the same and comprise 6 MOS tubes, and the first inverter comprises, The second inverter, the third inverter, the fourth inverter and the fifth inverter have the same internal structure and comprise 2 MOS tubes, an output node of the first exclusive-OR gate is connected with a first input node of the second exclusive-OR gate, an output node of the second exclusive-OR gate is connected with an input node of the first inverter, an output node of the third exclusive-OR gate is connected with a grid electrode of the first PMOS tube, a grid electrode of the first NMOS tube, a source electrode of the second PMOS tube and a source electrode of the second NMOS tube, a source electrode of the first PMOS tube is connected with an output node of the second inverter and a grid electrode of the second PMOS tube, a drain electrode of the first PMOS tube is connected with a drain electrode of the first NMOS tube, The drain electrode of the second PMOS tube, the drain electrode of the second NMOS tube, the source electrode of the third PMOS tube, the source electrode of the third NMOS tube and the second input node of the second exclusive-OR gate, the source electrode of the second NMOS tube is connected with the input node of the second inverter, the source electrode of the fifth PMOS tube and the source electrode of the fifth NMOS tube, the grid electrode of the third PMOS tube is connected with the grid electrode of the fourth NMOS tube and is controlled by the first input node of the second exclusive-OR gate, the drain electrode of the third PMOS tube is connected with the drain electrode of the third NMOS tube, the drain electrode of the fourth PMOS tube, the drain electrode of the fourth NMOS tube and the input node of the third inverter, the grid electrode of the third NMOS tube is connected with the grid electrode of the fourth PMOS tube, The source electrode of the fourth PMOS tube is connected with the source electrode of the fourth NMOS tube and is controlled by the first input node of the first XOR gate, the grid electrode of the fifth PMOS tube is connected with the grid electrode of the sixth NMOS tube and the output node of the fourth inverter, the drain electrode of the fifth PMOS tube is connected with the drain electrode of the fifth NMOS tube, the drain electrode of the sixth PMOS tube, the drain electrode of the sixth NMOS tube and the input node of the fifth inverter, the grid electrode of the fifth NMOS tube is connected with the grid electrode of the sixth PMOS tube, the output node of the third XOR gate, The source electrode of the sixth