CN-121979660-A - Data processing method, device, processor chip and computer system

Abstract

The disclosure relates to a data processing method, a data processing device, a processor chip and a computer system, and belongs to the technical field of computers. According to the method, the data processing device is used for providing the proxy cache of the system memory in the chip test stage, the source equipment is used for sending the read-write request for chip test to the data processing device, the data processing device is used for replacing the data read-write operation of the system memory into the proxy cache for carrying out the data read-write operation, the processor chip is not required to carry out the data read-write operation of the system memory, and the test of most functions in the processor chip is not required to depend on the system memory and is not required to be carried out after the system memory is debugged, so that the duration of the chip test stage can be reduced, and the test time before the mass production of the processor chip can be saved.

Inventors

• YANG KAIGE

Assignees

• 海光信息技术股份有限公司

Dates

Publication Date

20260505

Application Date

20251216

Claims (10)

1. 1. A data processing method, applied to a data processing device in a processor chip, the method comprising: receiving a read-write request of source equipment in a computer system, wherein the read-write request indicates to perform data read-write operation on a system memory in the computer system, and the read-write request is used for testing the processor chip; Based on the read-write request, performing data read-write operation on a first cache of the data processing device, wherein the first cache is an agent of the system memory in a chip test stage; And responding to the completion of the execution of the data read-write operation of the first cache, and sending a read-write response to the source equipment, wherein the read-write response indicates the completion of the execution of the read-write request.
2. 2. The method of claim 1, wherein the read-write request is a write request, the write request indicating writing test data to the system memory, the test data being used to test the processor chip; The performing data read-write operation on the first buffer memory of the data processing device based on the read-write request includes: and writing the test data into the first cache based on the write request.
3. 3. The method of claim 1, wherein the read-write request is a read request, the read request indicating to read test data from the system memory, the test data being used to test the processor chip; before receiving the read-write request of the source device in the processor chip, the method further comprises: Receiving a write request of the source device, the write request indicating writing the test data to the system memory; writing the test data to the first cache based on the write request; The performing data read-write operation on the first buffer memory of the data processing device based on the read-write request includes: based on the read request, the test data is read from the first cache.
4. 4. A method according to any of claims 1-3, characterized in that the data processing device further comprises a second cache for providing data cache services for read and write requests in the chip use phase.
5. 5. The method of claim 4, wherein the data processing device is a coherence controller or a memory controller in the processor chip, the memory controller being used to control the system memory, the coherence controller being a higher level controller of the memory controller.
6. 6. A data processing apparatus, comprising: The first cache is a proxy of the system memory in the chip test stage; A control circuit configured to perform the method of any one of claims 1-3.
7. 7. The data processing apparatus of claim 6, further comprising a second cache for providing data cache services for read and write requests during a chip use phase.
8. 8. The data processing apparatus of claim 7, wherein the data processing apparatus is a coherence controller or a memory controller in a processor chip, the memory controller being used to control the system memory, the coherence controller being a higher level controller of the memory controller.
9. 9. A processor chip comprising a processor core and the data processing apparatus of any of claims 6-8.
10. 10. A computer system comprising a system memory and a processor chip comprising a processor core and the data processing apparatus of any of claims 6-8.

Description

Data processing method, device, processor chip and computer system Technical Field The present disclosure relates to the field of computer technologies, and in particular, to a data processing method, a data processing device, a processor chip, and a computer system. Background Current computer systems generally include a processor chip and a system memory, and before the processor chip performs actual mass production, a large number of functional tests are required, where most of the tests require the processor chip to perform data read and write operations on the system memory. The component for initiating the read-write request in the processing chip is called a source device, the process of performing data read-write operation on the system memory by the processor chip needs to rely on an access link of 'source device in the processor chip-consistency controller in the processor chip-system memory', so most of the test of the processor chip needs to rely on the access link, and because the last node of the access link is the system memory, most of the test of the processor chip needs to wait for the completion of the debugging of the system memory and can be normally accessed by the system memory, the debugging of the system memory can be normally accessed is complex, and the time required for the debugging is long, which results in low chip test rate in a chip test stage and longer duration of the chip test stage, namely the test time before the mass production of the processor chip is longer. Disclosure of Invention The disclosure provides a data processing method, a data processing device, a processor chip and a computer system, so as to at least solve the problem that the duration of a chip test stage in the related art is relatively long. The technical scheme of the present disclosure is as follows: according to a first aspect of embodiments of the present disclosure, there is provided a data processing method, A data processing apparatus for use in a processor chip, the method comprising: receiving a read-write request of source equipment in a computer system, wherein the read-write request indicates to perform data read-write operation on a system memory in the computer system, and the read-write request is used for testing the processor chip; Based on the read-write request, performing data read-write operation on a first cache of the data processing device, wherein the first cache is an agent of the system memory in a chip test stage; And responding to the completion of the execution of the data read-write operation of the first cache, and sending a read-write response to the source equipment, wherein the read-write response indicates the completion of the execution of the read-write request. Optionally, the read-write request is a write request, the write request indicates writing test data to the system memory, and the test data is used for testing the processor chip; The performing data read-write operation on the first buffer memory of the data processing device based on the read-write request includes: and writing the test data into the first cache based on the write request. Optionally, the read-write request is a read request, the read request indicating reading test data from the system memory, the test data being used for testing the processor chip; before receiving the read-write request of the source device in the processor chip, the method further comprises: Receiving a write request of the source device, the write request indicating writing the test data to the system memory; writing the test data to the first cache based on the write request; The performing data read-write operation on the first buffer memory of the data processing device based on the read-write request includes: based on the read request, the test data is read from the first cache. Optionally, the data processing apparatus further includes a second buffer, where the second buffer is configured to provide a data buffer service for read-write requests in the chip usage stage. Optionally, the data processing device is a coherence controller or a memory controller in the processor chip, where the memory controller is used to control the system memory, and the coherence controller is a controller at a level higher than the memory controller. According to a second aspect of embodiments of the present disclosure, there is provided a data processing apparatus comprising: The first cache is a proxy of the system memory in the chip test stage; A control circuit configured to perform the data processing method of the first aspect or any of the possible implementation manners of the first aspect. According to a third aspect of embodiments of the present disclosure, there is provided a processor chip comprising a processor core and the data processing apparatus provided in the second aspect above. According to a fourth aspect of embodiments of the present disclosure, there is provided a computer system comprising a system mem