Search

CN-121979662-A - Data processing method, consistency controller, processor chip and computer system

CN121979662ACN 121979662 ACN121979662 ACN 121979662ACN-121979662-A

Abstract

The disclosure relates to a data processing method, a consistency controller, a processor chip and a computer system, and belongs to the technical field of computers. According to the method, the completion queue is additionally arranged in the consistency controller, after the access request is executed, the consistency controller can release the space occupied by the related information of the access request in the request queue only by storing the execution completion information of the access request into the completion queue without waiting for the end of the processing flow of the access request, so that the occupied time of a single access request to the request queue is reduced, the request queue can provide cache service for more access requests, and the utilization rate of the request queue can be improved.

Inventors

  • YANG KAIGE

Assignees

  • 海光信息技术股份有限公司

Dates

Publication Date
20260505
Application Date
20251216

Claims (10)

  1. 1. A data processing method for use with a coherence controller in a processor chip, the method comprising: receiving an access request of source equipment; Storing the related information of the access request to a request queue of the consistency controller; executing the access request; And responding to the execution completion of the access request, storing the execution completion information of the access request into a completion queue of the consistency controller, releasing the space occupied by the related information in the request queue, and sending an execution completion response to the source equipment, wherein the execution completion response and the execution completion information both indicate that the access request is completed.
  2. 2. The method of claim 1, wherein the access request includes a target memory address, the access request indicating access to a memory space indicated by the target memory address; the execution completion information includes an identification of the access request and the target memory address.
  3. 3. The method according to claim 1, wherein the method further comprises: Storing target data into a cache of the consistency controller, wherein the target data is data which is requested to be read or written by the access request; and responding to the completion of the execution of the access request, and releasing the space occupied by the target data in the cache.
  4. 4. A method according to any one of claims 1-3, characterized in that the method further comprises: And in response to receiving a confirmation message of the source equipment for the execution completion response, releasing the space occupied by the execution completion information in the completion queue, wherein the confirmation message indicates the source equipment to confirm that the execution completion response is received.
  5. 5. A coherence controller comprising control circuitry, a request queue, and a completion queue, the control circuitry configured to perform: receiving an access request of source equipment; storing the related information of the access request to the request queue; executing the access request; And responding to the execution completion of the access request, storing the execution completion information of the access request into the completion queue, releasing the space occupied by the related information in the request queue, and sending an execution completion response to the source equipment, wherein the execution completion response and the execution completion information both indicate that the access request is completed.
  6. 6. The coherence controller of claim 5, wherein said access request comprises a target memory address, said access request indicating access to a memory space indicated by said target memory address; the execution completion information includes an identification of the access request and the target memory address.
  7. 7. The coherence controller of claim 5, further comprising a cache, said control circuit further configured to perform: Storing target data into the cache, wherein the target data is data which is requested to be read or written by the access request; and responding to the completion of the execution of the access request, and releasing the space occupied by the target data in the cache.
  8. 8. The coherence controller of any one of claims 5-7, wherein said control circuit is further configured to perform: And in response to receiving a confirmation message of the source equipment for the execution completion response, releasing the space occupied by the execution completion information in the completion queue, wherein the confirmation message indicates the source equipment to confirm that the execution completion response is received.
  9. 9. A processor chip comprising a processor core and the coherence controller of any one of claims 5-8.
  10. 10. A computer system comprising a system memory and a processor chip comprising a processor core and the coherence controller of any one of claims 5-8.

Description

Data processing method, consistency controller, processor chip and computer system Technical Field The present disclosure relates to the field of computer technologies, and in particular, to a data processing method, a coherence controller, a processor chip, and a computer system. Background Current computer systems include a plurality of processor cores, input Output (IO) devices, and a coherence controller to maintain cache coherence among the plurality of processor cores. The processor core and the IO device in the computer system can send an access request to the consistency controller, and the access request is uniformly processed by the consistency controller. Taking the processing of the access request of the processor core as an example, currently, the process of processing the access request by the consistency controller may be that the consistency controller receives the access request of the processor core, stores the related information of the access request into a request queue of the consistency node, executes the access request, returns an execution completion response of the access request to the processor core after the execution of the access request is completed, and after the processor core confirms that the execution completion response is received, the consistency controller finishes the processing flow of the access request and releases the space occupied by the related information of the access request in the request queue. Because the coherence controller can not release the space occupied by the related information of the access request in the request queue until the processing flow of the access request is finished, the occupation time of a single access request on the request queue is too long, and the request queue can not provide cache service for more access requests, so that the utilization rate of the request queue is low. Disclosure of Invention The present disclosure provides a data processing method, a coherence controller, a processor chip and a computer system, so as to at least solve the problem of low utilization of a request queue of the coherence controller in the related art. The technical scheme of the present disclosure is as follows: According to a first aspect of embodiments of the present disclosure, there is provided a data processing method applied to a coherence controller in a processor chip, the method comprising: receiving an access request of source equipment; Storing the related information of the access request to a request queue of the consistency controller; executing the access request; And responding to the execution completion of the access request, storing the execution completion information of the access request into a completion queue of the consistency controller, releasing the space occupied by the related information in the request queue, and sending an execution completion response to the source equipment, wherein the execution completion response and the execution completion information both indicate that the access request is completed. Optionally, the access request includes a target memory address, and the access request indicates to access a memory space indicated by the target memory address; the execution completion information includes an identification of the access request and the target memory address. Optionally, the method further comprises: Storing target data into a cache of the consistency controller, wherein the target data is data which is requested to be read or written by the access request; and responding to the completion of the execution of the access request, and releasing the space occupied by the target data in the cache. Optionally, the method further comprises: And in response to receiving a confirmation message of the source equipment for the execution completion response, releasing the space occupied by the execution completion information in the completion queue, wherein the confirmation message indicates the source equipment to confirm that the execution completion response is received. According to a second aspect of embodiments of the present disclosure, there is provided a coherence controller comprising control circuitry, a request queue and a completion queue, the control circuitry being configured to perform: receiving an access request of source equipment; storing the related information of the access request to the request queue; executing the access request; And responding to the execution completion of the access request, storing the execution completion information of the access request into the completion queue, releasing the space occupied by the related information in the request queue, and sending an execution completion response to the source equipment, wherein the execution completion response and the execution completion information both indicate that the access request is completed. Optionally, the access request includes a target memory address, and the access request indicates to access