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CN-121979663-A - Data processing method, device, processor chip and computer system

CN121979663ACN 121979663 ACN121979663 ACN 121979663ACN-121979663-A

Abstract

The disclosure relates to a data processing method, a data processing device, a processor chip and a computer system, and belongs to the technical field of computers. According to the method, the storage position of the data to be mirrored in the memory and the storage position of the mirrored data of the data in the memory are respectively designated through the mirrored address segment and the mirrored address segment in the preset address segment, and the positions and the sizes indicated by the mirrored address segment and the mirrored address segment are variable, so that the mirrored memory can be flexibly set for the data to be mirrored through the preset address pair, relatively low-reliability data in the computer system can be ignored, only the data with relatively high reliability in the computer system are used as the data to be mirrored, and the mirrored memory is set for the data to be mirrored through the preset address pair, so that the memory space of the memory in the computer system can be utilized to the maximum, and the hardware cost of the memory in the computer system is reduced.

Inventors

  • YANG KAIGE
  • CAO JUN

Assignees

  • 海光信息技术股份有限公司

Dates

Publication Date
20260505
Application Date
20251216

Claims (14)

  1. 1. A data processing method for use with a first processor chip in a computer system, the method comprising: Acquiring a first write request, wherein the first write request indicates to write first data into a memory space indicated by a first memory address segment in the computer system; writing the first data into the memory space indicated by the first memory address segment; Determining whether the first memory address segment belongs to a mirrored address segment based on at least one preset address pair, wherein the preset address pair comprises the mirrored address segment and a mirrored address segment of the mirrored address segment, the mirrored address segment is used for storing data to be mirrored in the computer system, and the mirrored address segment is used for storing mirrored data of the data; And if the first memory address segment belongs to the mirrored address segment, writing the mirrored data of the first data into a memory space indicated by the mirrored address segment of the first memory address segment, wherein the mirrored address segment of the first memory address segment belongs to the mirrored address segment of the mirrored address segment to which the first memory address segment belongs.
  2. 2. The method of claim 1, wherein the mirrored address segment and the mirrored address segment are the same length.
  3. 3. The method of claim 1, wherein the mirrored address segment to which the first memory address segment belongs corresponds to a first memory channel in the first processor chip, and wherein the mirrored address segment of the first memory address segment corresponds to a second memory channel in the first processor chip; The writing the first data to the memory space indicated by the first memory address segment includes: writing the first data into the memory space indicated by the first memory address segment through the first memory channel; If the first memory address segment belongs to the mirrored address segment, writing the mirrored data of the first data into the memory space indicated by the mirrored address segment of the first memory address segment, including: And if the first memory address segment belongs to the mirrored address segment, writing mirrored data of the first data into a memory space indicated by the mirrored address segment of the first memory address segment through the second memory channel.
  4. 4. The method of claim 1, wherein the computer system comprises a second processor chip, wherein the mirrored address segment to which the first memory address segment belongs corresponds to a first memory channel in the first processor chip, and wherein the mirrored address segment of the first memory address segment corresponds to a memory channel in the second processor chip; The writing the first data to the memory space indicated by the first memory address segment includes: writing the first data into the memory space indicated by the first memory address segment through the first memory channel; If the first memory address segment belongs to the mirrored address segment, writing the mirrored data of the first data into the memory space indicated by the mirrored address segment of the first memory address segment, including: and if the first memory address segment belongs to the mirrored address segment, sending a second write request to the second processor chip, wherein the second write request indicates to write the mirrored data of the first data into the memory space indicated by the mirrored address segment of the first memory address segment.
  5. 5. The method according to any of claims 1-4, wherein the at least one preset address pair is set based on traffic demand for mirrored data.
  6. 6. A data processing method for use with a first processor chip in a computer system, the method comprising: Acquiring a first read request, wherein the first read request indicates that second data is read from a memory space indicated by a second memory address segment in the computer system; Reading the second data from the memory space indicated by the second memory address segment; If a data reading error occurs during reading the second data, determining whether the second memory address segment belongs to a mirrored address segment based on at least one preset address pair, wherein the preset address pair comprises the mirrored address segment and a mirrored address segment of the mirrored address segment, the mirrored address segment is used for storing mirrored data in the computer system, and the mirrored address segment is used for storing mirrored data of the mirrored data; if the second memory address segment belongs to the mirrored address segment, reading the mirrored data of the second data from the memory space indicated by the mirrored address segment of the second memory address segment, wherein the mirrored address segment of the second memory address segment belongs to the mirrored address segment of the mirrored address segment to which the second memory address segment belongs; And transmitting the read mirror image data of the second data.
  7. 7. The method of claim 6, wherein the mirrored address segment and the mirrored address segment are the same length.
  8. 8. The method of claim 6, wherein the mirrored address segment to which the second memory address segment belongs corresponds to a third memory channel in the first processor chip, and wherein the mirrored address segment of the second memory address segment corresponds to a fourth memory channel in the first processor chip; The reading the second data from the memory space indicated by the second memory address segment includes: Reading the second data from the memory space indicated by the second memory address segment through the third memory channel; and if the second memory address segment belongs to the mirrored address segment, reading the mirrored data of the second data from the memory space indicated by the mirrored address segment of the second memory address segment, including: And if the second memory address segment belongs to the mirrored address segment, reading the mirrored data of the second data from the memory space indicated by the mirrored address segment of the second memory address segment through the fourth memory channel.
  9. 9. The method of claim 6, wherein the computer system includes a third processor chip, wherein the mirrored address segment to which the second memory address segment belongs corresponds to a first memory channel in the first processor chip, and wherein the mirrored address segment of the second memory address segment corresponds to a memory channel in the third processor chip; The reading the second data from the memory space indicated by the second memory address segment includes: Reading the second data from the memory space indicated by the second memory address segment through the third memory channel; and if the second memory address segment belongs to the mirrored address segment, reading the mirrored data of the second data from the memory space indicated by the mirrored address segment of the second memory address segment, including: and if the second memory address segment belongs to the mirrored address segment, sending a second read request to the third processor chip, wherein the second read request indicates that mirror data of the second data is read from a memory space indicated by the mirrored address segment of the second memory address segment.
  10. 10. The method according to any of claims 6-9, wherein the at least one preset address pair is set based on traffic demand for mirrored data.
  11. 11. A data processing apparatus comprising a cache for storing data and a control circuit configured to perform the data processing method of any one of claims 1 to 10.
  12. 12. The data processing apparatus of claim 11, wherein the data processing apparatus is a coherence controller or a memory controller in a processor chip, the memory controller being configured to control a memory chip, the coherence controller being a higher level controller of the memory controller.
  13. 13. A processor chip comprising a processor core and the data processing apparatus of claim 11 or 12.
  14. 14. A computer system comprising a memory chip for storing data written by the processor chip and the processor chip of claim 13.

Description

Data processing method, device, processor chip and computer system Technical Field The present disclosure relates to the field of computer technologies, and in particular, to a data processing method, a data processing device, a processor chip, and a computer system. Background Current computer systems include a processor chip and a plurality of memory chips, each processor chip including a plurality of memory channels, each memory channel connecting at least one memory chip. In order to backup data, at present, with the memory channel as granularity, one part of memory chips in the plurality of memory chips is set as a main memory of the computer system, and the other part of memory chips is set as mirror memory of the main memory. For example, the processor chip includes a memory channel 1 and a memory channel 2, each memory chip connected to the memory channel 1 is set as a main memory, and each memory chip connected to the memory channel 2 is set as a mirror memory of the main memory. When the processor chip stores the data into the main memory, the mirror image data of the data is also stored into the mirror image memory so as to backup the data in the mirror image memory. However, the data to be backed up is generally data with high reliability (i.e. data with high reliability), but the data in the main memory does not have high reliability, and in general, the data with high reliability in the main memory occupies less space in the mirror memory, i.e. the data with high reliability in the main memory occupies less space in the mirror memory. In the backup scheme, when the mirror memory is set by taking the memory channel as granularity, the requirement of data on reliability is not considered, when the data is stored in the main memory, the mirror data of the data is also stored in the mirror memory, so that some data with low requirement on reliability in the main memory can be backed up in the mirror memory, and the memory space of the mirror memory is occupied, thereby causing the waste of the memory space. Disclosure of Invention The disclosure provides a data processing method, a data processing device, a processor chip and a computer system, which can reduce the waste of the memory space of the computer system. The technical scheme of the present disclosure is as follows: According to a first aspect of embodiments of the present disclosure, there is provided a data processing method applied to a first processor chip in a computer system, the method including: Acquiring a first write request, wherein the first write request indicates to write first data into a memory space indicated by a first memory address segment in the computer system; writing the first data into the memory space indicated by the first memory address segment; Determining whether the first memory address segment belongs to a mirrored address segment based on at least one preset address pair, wherein the preset address pair comprises the mirrored address segment and a mirrored address segment of the mirrored address segment, the mirrored address segment is used for storing data to be mirrored in the computer system, and the mirrored address segment is used for storing mirrored data of the data; And if the first memory address segment belongs to the mirrored address segment, writing the mirrored data of the first data into a memory space indicated by the mirrored address segment of the first memory address segment, wherein the mirrored address segment of the first memory address segment belongs to the mirrored address segment of the mirrored address segment to which the first memory address segment belongs. Optionally, the mirrored address segment and the mirrored address segment have the same length. Optionally, the mirrored address segment to which the first memory address segment belongs corresponds to a first memory channel in the first processor chip, and the mirrored address segment of the first memory address segment corresponds to a second memory channel in the first processor chip; The writing the first data to the memory space indicated by the first memory address segment includes: writing the first data into the memory space indicated by the first memory address segment through the first memory channel; If the first memory address segment belongs to the mirrored address segment, writing the mirrored data of the first data into the memory space indicated by the mirrored address segment of the first memory address segment, including: And if the first memory address segment belongs to the mirrored address segment, writing mirrored data of the first data into a memory space indicated by the mirrored address segment of the first memory address segment through the second memory channel. Optionally, the computer system includes a second processor chip, the mirrored address segment to which the first memory address segment belongs corresponds to a first memory channel in the first processor chip, and the mirrored address seg