Search

CN-121979709-A - SRIO-based anti-single particle reinforcement method for satellite-borne processor

CN121979709ACN 121979709 ACN121979709 ACN 121979709ACN-121979709-A

Abstract

The invention relates to a satellite-borne processor single event resistance reinforcement method based on SRIO, which belongs to the technical field of spaceflight embedded software, wherein between a processor supporting the SRIO and an FPGA, the FPGA reads P CPU from a processor program storage area according to the agreed package size through an SRIO interface, meanwhile, the backup package P 1 、P 2 、P 3 at the corresponding position is read from the backup area and is subjected to bit three-in-two calculation to obtain a calculation result P S , then P S is compared with P CPU and P 1 、P 2 、P 3 , and when errors are found, P S is used for error correction and overwriting. And refreshing and correcting the running program in the multi-core processor and maintaining the correctness of the backup area by sequentially routing inspection of the program storage areas of the processor cores packet by packet. When a P CPU error is found, a prioritized global check of the error core may be triggered.

Inventors

  • YUAN YUAN
  • DONG GUOWEI
  • PAN ZHENG
  • WU YUWEI
  • TANG QI
  • Zhou haian
  • Liu Modan
  • LIU MING
  • Nan Nuo
  • LI XIN
  • WANG ZHEN
  • MOU YANNA

Assignees

  • 北京空间机电研究所

Dates

Publication Date
20260505
Application Date
20251219

Claims (10)

  1. 1. The SRIO-based satellite-borne processor single particle resistance reinforcement method is characterized by comprising the following steps of: (1) Setting a patrol function module mode by the processor, and configuring patrol cycle, the number of patrol packets per cycle and the like of the patrol function module; (2) Initializing a patrol functional module through patrol parameters stored in the FPGA; (3) The inspection functional module establishes a memory mapping relation between the running address of each processor core program and program images in the nonvolatile memory and the plug-in RAM according to inspection parameters, copies 3 program images into the plug-in RAM, and obtains 3 groups of backups of the processor programs; (4) The inspection functional module starts to operate based on the configuration parameters obtained in the step (1), inspects the core 0, and compares and corrects the backup program package and the processor program package after triggering by the trigger signal; (5) Repeating the step (4) until the inspection of the number of remaining inspection packets in the period of the core 0 is completed; (6) And (5) repeating the steps (4) to (5), and sequentially completing the inspection of the core program storage areas of other processors.
  2. 2. The SRIO-based satellite-borne processor anti-single particle reinforcement method according to claim 1, wherein embedded software triple-mode operated by the processor is stored in a nonvolatile memory hung on the FPGA, and the FPGA can control reset starting of the processor.
  3. 3. The method for resisting single event reinforcement of a satellite-borne processor based on SRIO according to claim 2, wherein the inspection parameters are stored in the nonvolatile memory in a three-mode, and the inspection parameters comprise an operation start address of a processor core program, a program mirror image storage start address and an inspection length.
  4. 4. The SRIO-based satellite-borne processor single event reinforcement method of claim 1, wherein in the step (1), the inspection function module mode comprises error reporting only without correction, manual correction and automatic correction.
  5. 5. The SRIO-based satellite-borne processor single event reinforcement method according to claim 1, wherein in the step (2), the inspection function module reads 3 inspection parameters, performs three-two calculation, performs format verification inspection on a calculation result, initializes the inspection function module by using the calculation result parameters if the calculation result parameters are correct, and sets the initialization state of the inspection function module as abnormal if the calculation result parameters are incorrect.
  6. 6. The SRIO-based anti-single particle reinforcement method for the satellite-borne processor, as set forth in claim 1, is characterized in that in the step (3), the plug-in RAM is a DDR memory.
  7. 7. The method for resisting single event reinforcement of a satellite-borne processor based on SRIO as set forth in claim 1, wherein in the step (4), the inspection method is as follows, when the trigger signal triggers, the inspection function module reads the backup packet P 1_CORE0_0 、P 2_CORE0_0 、P 3_CORE0_0 of the core 0 packet number 0 from the backup obtained in the step (3), obtains the packet P S_CORE0_0 through two-from-three calculation, reads the corresponding first packet P CPU_CORE0_0 from the core 0 program operation starting address through SRIO, then performs data comparison, if the packet P CPU_CORE0_0 is consistent with the packet P S_CORE0_0 , the packet is correct, if the packet P CPU_CORE0_0 is inconsistent with the packet P S_CORE0_0 , the packet P S_CORE0_0 is written back to the corresponding position of the processor through SRIO to complete error correction, and similarly, if the backup packets P 1_CORE0_0 、P 2_CORE0_0 and P 3_CORE0_0 are both consistent with the packet P S_CORE0_0 , the packet is correct, if the backup packet P 1_CORE0_0 、P 2_CORE0_0 or the backup packet P 3_CORE0_0 is inconsistent with the packet P S_CORE0_0 , the packet P S_CORE0_0 is erroneous, and the packet is written back to the corresponding position of the backup packet to complete error correction.
  8. 8. The SRIO-based satellite-borne processor single particle reinforcement method of claim 1 is characterized in that the inspection processes of different cores are independently completed in turn.
  9. 9. The SRIO-based satellite-borne processor single event reinforcement method according to claim 1, wherein if a program package of a certain core x detects an error, the comprehensive inspection of the core x is preferentially performed according to an inspection strategy configured by an inspection functional module.
  10. 10. An SRIO-based satellite-borne processor is characterized in that the satellite-borne processor is reinforced by the reinforcement method according to any one of claims 1-9.

Description

SRIO-based anti-single particle reinforcement method for satellite-borne processor Technical Field The invention belongs to the technical field of aerospace embedded software, and particularly relates to an SRIO-based anti-single particle reinforcement method for a satellite-borne processor. Background In the aerospace field, heterogeneous multi-core architecture adopting a processor and an FPGA in space-borne equipment has been widely applied. However, the spacecraft is influenced by high-energy particle radiation existing in a space environment in the on-orbit running process, so that certain bit positions of the embedded software running by the processor can be overturned, the running abnormality of the embedded software is further caused, and the function of the equipment is interrupted. Common anti-SEU (SINGLE EVENT Upset ) measures include redundancy design, hardware reinforcement, software reinforcement, etc., to improve operational reliability and fault tolerance. The method is limited by the requirements of short development period, high performance, low cost and the like of the satellite-borne equipment, and when the non-aerospace-level processor is selected for the development of the satellite-borne equipment, the processor is difficult to resist space high-energy particles due to insufficient radiation resistant design, so that SEU occurs in a storage unit or a logic circuit of the processor, and the reliable operation of the equipment is seriously influenced. Generally speaking, a non-aerospace level processor does not have corresponding hardware EDAC (Error Detection And Correction ), or the hardware EDAC has insufficient error correction capability (usually only supporting correction 1, detection 2), and cannot correct or even detect multi-bit flip occurring in a single error correction detection region. Technology for realizing single event resistance of processor through software reinforcement at home and abroad is generally NVersion method, recovery block method, software simulation EDAC method, EDDI and ED4I fault tolerance algorithm, etc. all need to occupy processor operation resource, not only increasing complexity of software development, but also increasing time and space overhead of processor. The SRIO (Serial RapidIO) protocol is a high-reliability, high-performance and high-speed interconnection technology based on packet switching, which is proposed for an embedded system, and can establish a low-delay high-speed transmission channel between a processor supporting SRIO and an FPGA. The FPGA can initiate direct memory access transmission to the processor through SRIO, and achieve non-inductive read-write operation to the processor memory. The patent 'soft error real-time error detection and recovery method and system for online parallel processing' (publication number CN 112053737A) is connected to a processor through a high-speed interface by an FPGA, and uses various check codes to carry out parallel comparison and error detection on protected RAM space and backup of the processor, realize error positioning and carry out recovery processing. The method mainly realizes the confirmation of the correct data block and the detection of the abnormal data block through the consistency comparison of the check codes, uses the correct data to cover the error data, has more complex error judgment and processing logic, has certain defects in error correction, for example, when the different bits of each backup same data block have errors, the correct data block cannot be found, the abnormal data cannot be recovered, the error correction fails, the single particle risk faced by the FPGA operation in the complex environment is not considered, and the single particle resistance measures are lacked. Disclosure of Invention The invention aims to provide an SRIO-based satellite-borne processor single-particle-resistant reinforcement method, which is characterized in that an FPGA directly carries out inspection on a processor running program through an SRIO interface, and program errors caused by single-particle overturn are detected and corrected in time, so that the error accumulation risk is reduced, and the reliability of the processor software in the running process can be obviously improved at a lower resource cost. The above object of the present invention is mainly achieved by the following technical solutions: An SRIO-based anti-single particle reinforcement method for a satellite-borne processor comprises the following steps: (1) Setting a patrol function module mode by the processor, and configuring patrol cycle, the number of patrol packets per cycle and the like of the patrol function module; (2) Initializing a patrol functional module through patrol parameters stored in the FPGA; (3) The inspection function module establishes a memory mapping relation between the running address of each processor core program and program images in the nonvolatile memory and the plug-in RAM according