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CN-121979729-A - Chip system with built-in interconnection test and repair functions and method thereof

CN121979729ACN 121979729 ACN121979729 ACN 121979729ACN-121979729-A

Abstract

The invention discloses a three-dimensional packaging chip system with built-in interconnection test function and a detection method thereof, wherein the system comprises a packaging semiconductor body internally provided with a plurality of wiring layers, a design for testability (DFT) circuit integrated in a chip, an internal multichannel selective switch network controlled by the DFT circuit and arranged on each wiring layer, and at least two pins/bonding pads which are arranged outside the packaging, have small quantity and have increased pin spacing. According to the method, the DFT circuit is used for controlling the switching network to switch, different internal interconnection paths are multiplexed to the detection points in a time-sharing mode to perform electrical measurement, and the accurate positioning of fault nodes is achieved by analyzing multiple groups of measurement results. The invention effectively solves the problem of difficult pin card test caused by warpage of high-density package, realizes layering and node precise diagnosis of interconnection faults inside the three-dimensional package for the first time, obviously reduces test cost and complexity, and provides a hardware foundation for on-line function repair.

Inventors

  • HOU JIANFEI
  • SHEN HAIBING

Assignees

  • 天衡半导体科技(苏州)有限公司

Dates

Publication Date
20260505
Application Date
20260124

Claims (10)

  1. 1. A three-dimensional packaged chip system with built-in interconnect testing function, comprising: a packaged semiconductor body including a plurality of wiring layers therein; a testability design circuit integrated within the packaged semiconductor body; an internal multi-channel selection switch network arranged in the multi-layer wiring layer and controlled by the testability design circuit for dynamically configuring interconnection paths in and between the wiring layers; At least two pins/pads for detection, which are arranged outside the packaged semiconductor body and are electrically connected to the testability design circuit; In the test mode, the testability design circuit can connect different internal interconnection paths to the at least two pins/pads in a time-sharing multiplexing manner by controlling the switching of the internal multi-channel selection switch network, so that the electrical test and fault positioning of all selected interconnection paths are completed through the pins/pads for detection.
  2. 2. The three-dimensional packaged chip system of claim 1, wherein adjacent pin center distances of said at least two sense pins/pads are greater than adjacent pin center distances of functional pins on said packaged semiconductor body.
  3. 3. The three-dimensional packaged chip system of claim 1 or 2, wherein the internal multi-channel selection switch network comprises a micro-switch unit disposed between a signal via and a standby via of the multilayer wiring layer.
  4. 4. The three-dimensional packaged chip system of claim 1, further comprising a pin-level multi-channel select switch disposed at an input/output interface for selectively connecting internal signals to different physical function pins, and wherein the pin-level multi-channel select switch is controlled by the design for testability circuit.
  5. 5. The three-dimensional packaged chip system of claim 1, wherein the testability design circuit is a scan test structure, a built-in self-test controller, or a test access port controller.
  6. 6. An interconnection detection method based on the three-dimensional package chip system of any one of claims 1 to 5, characterized by comprising the steps of: S1, configuring a test path, namely sending a control instruction to the testability design circuit through the detection pin/bonding pad to control the internal multi-channel selection switch network to form a first test path, wherein the first test path is connected with at least one section of internal interconnection path to be tested in series; S2, electrical measurement, namely applying a test signal to the first test path through the detection pin/bonding pad, and acquiring an electrical response of the test signal to judge the communication state of the path; s3, path scanning, namely repeating the steps S1 and S2, and forming and measuring a plurality of different test paths by changing the configuration of the internal multi-channel selection switch network until all target interconnection paths are covered; S4, fault positioning, namely analyzing measurement results of all the test paths, and positioning a specific node with faults and a wiring layer where the specific node is located by comparing interconnection nodes contained in different paths.
  7. 7. The interconnect detection method of claim 6, wherein after locating the failed node in step S4, the method further comprises: and repairing and configuring, namely if a preset standby path exists, controlling the internal multi-channel selection switch network through the testability design circuit, and switching a signal path affected by the fault to the standby path.
  8. 8. The interconnect detection method of claim 6, wherein when the system comprises the pin-level multi-channel select switch of claim 4, the method further comprises: and pin repair, namely when the fault of the pin with the specific function is detected, controlling the pin-level multichannel selection switch through the testability design circuit, and switching the internal signal to the normal spare function pin.
  9. 9. The interconnect inspection method of claim 6, wherein the test signal in step S2 is a direct current or a low frequency alternating current signal, and the electrical response is a resistance value or a voltage drop of a path.
  10. 10. The interconnect inspection method of claim 6, wherein the number of inspection pins/pads is two, serving as a test stimulus application terminal and a test response receiving terminal, respectively.

Description

Chip system with built-in interconnection test and repair functions and method thereof Technical Field The present invention relates to the field of semiconductor integrated circuit manufacturing and testing technology, and in particular, to a chip system that integrates design for testability (DFT) circuits with a reconfigurable interconnect network during a chip design stage. The system can complete quick electrical test, accurate positioning and online repair of all interconnection paths in the multi-pin and multi-layer stacked package structure through a few external test points, and is particularly suitable for solving the industrial problems of difficult pin card test and irreparable internal faults caused by warpage in advanced packaging. Background Along with the gradual approach of moore's law to physical limit, the realization of heterogeneous integration and performance improvement by advanced technologies such as three-dimensional stacked packaging, through Silicon Vias (TSVs), system-in-package and the like has become the mainstream development direction of the semiconductor industry. However, these advanced packaging techniques introduce unprecedented testing challenges, mainly focused on the complexity, cost, and reliability of interconnect testing, embodied as: The test access challenge with high density external pins is that three-dimensional packaged chips typically have hundreds or even thousands of high density arranged input/output (I/O) pins (e.g., solder balls) with a pitch of as little as 0.3mm or less. Electrical testing of such chips necessitates the use of corresponding high density probe cards or test sockets. These precision jigs are not only extremely expensive to manufacture, but also extremely demanding in terms of coplanarity (warpage) of the package. In actual production, the package body generates micron-sized warpage due to mismatch of thermal expansion coefficients of materials or process stress, which is very common, and is very easy to cause poor contact between a probe and a pin, cause erroneous test judgment (judging good products as bad products), or cause damage to a probe card, and cause huge equipment loss and production delay. The "black box" dilemma of internal interconnect failures, where traditional external testing methods, such as boundary scan (JTAG), focus primarily on the functionality of the logic core inside the chip, can only provide extremely limited "pass/fail" information for the health status of the physical interconnects inside the package, including inter-layer through silicon vias, re-wiring layer (RDL) traces, microbumps, etc. Once the test fails, it cannot be determined at which layer of wiring, which specific path, which connection node the fault occurred. The black box characteristic makes the process problem difficult to locate, the failure analysis cost is high, and the defects which can be partially repaired cannot be screened. Contradiction of test coverage and efficiency in order to detect internal interconnect defects as much as possible, complex test excitation and measurement schemes may need to be designed, but this often requires the occupation of a large number of functional pins or the addition of additional test pins, contrary to the miniaturization trend of packages. Meanwhile, the pin-by-pin testing is long in time consumption, and the throughput of the production line is affected. The lack of on-line repair capability is that at present, once physical damages such as circuit breaking, short circuit and the like occur in production test or later use, the interconnections inside the package are regarded as permanent failures, and the whole chip module is scrapped. For advanced packaging products, which are costly, this results in serious yield loss and resource waste. Therefore, there is a need in the industry for an innovative test architecture that can fundamentally simplify the external test interface, achieve accurate perspective and positioning of internal interconnections, and provide potential repair capabilities. . Disclosure of Invention The primary object of the present invention is to overcome the above-mentioned drawbacks of the prior art, and to provide an innovative three-dimensional package chip system and a detection method thereof, which aims at: The special external test points with extremely small design quantity and enlarged pin spacing are adopted, so that the dependence on a high-cost and high-precision probe card is thoroughly eliminated, and the simplification and the robustness of the test interface are realized. By embedding design for testability (DFT) circuitry and reconfigurable interconnect switching network in the chip design stage, addressable, time-division multiplexed testing of all critical interconnect paths inside the package is achieved and faults can be precisely located to specific routing layers and physical nodes. The intelligent detection method based on the hardware structure not onl