CN-121979731-A - Fault testing method and system based on hardware-in-loop simulation

CN121979731ACN 121979731 ACN121979731 ACN 121979731ACN-121979731-A

Abstract

The invention relates to the technical field of hardware-in-loop simulation, and discloses a fault test method and system based on hardware-in-loop simulation, wherein the method comprises the following steps of inputting test data information into an HIL rack and storing the test data information into a test database; analyzing the test requirement into a plurality of functional modules, matching the test items with the injection faults of the HIL rack to generate test cases and storing the test cases in a test database, carrying out modularized packaging on fault injection control codes according to the HIL rack information and a software framework, storing the modularized packaged fault injection control codes in the test database by using a file format, associating the test steps of the test cases in the test database with the modularized packaged fault injection control codes to generate test codes, and executing the test codes on the HIL rack to generate test results. The invention solves the problems of low automation degree, low testing efficiency and the like in the prior art.

Inventors

ZHANG YI
YANG BING
HUANG LANG
QI JIANING

Assignees

辰致科技有限公司

Dates

Publication Date: 20260505
Application Date: 20251204

Claims (10)

1. The fault test method based on hardware-in-the-loop simulation is characterized by comprising the following steps of: Inputting test data information into the HIL rack and storing the test data information into a test database, wherein the test data information comprises test requirements, a software framework and HIL rack information; Analyzing the test requirement into a plurality of functional modules, wherein each functional module comprises one or more test items, matching the test items with the injection faults of the HIL rack, generating test cases and storing the test cases in a test database, and the test cases comprise one or more test steps; According to HIL rack information and a software framework, carrying out modularized packaging on the fault injection control codes, and storing the modularized packaged fault injection control codes into a test database by using a file format; and executing the test code on the HIL rack to generate a test result.
2. The fault testing method based on hardware-in-the-loop simulation according to claim 1, wherein the test requirements are parsed into a plurality of functional modules, each functional module comprising one or more test items, comprising the steps of: and according to different test case code templates in the test database, disassembling the test requirements into independent test items.
3. The fault testing method based on hardware-in-the-loop simulation according to claim 2, wherein the step of disassembling the test requirements into independent test items according to different test case code templates in the test database comprises the following steps: Analyzing the test requirement into a test case keyword by a finite state method; searching a test case code template in a test database through the test case keywords; And filling keyword information in the test case code template to generate a test case.
4. A hardware-in-the-loop simulation based fault testing method as claimed in claim 3, wherein the test case code templates are updated as test requirements increase.
5. The method for testing a fault based on hardware-in-the-loop simulation of claim 4, wherein when the fault injection control code is modularly packaged, the fault injection control code is packaged as one or more functions, each corresponding to a test step.
6. The hardware-in-the-loop simulation based fault testing method as claimed in claim 5, wherein the step of associating the test steps of the test cases in the test database with the fault injection control codes after the modular packaging to generate the test codes comprises the steps of: Associating test steps of test cases in a test database with fault injection control codes; C, generating a code which can be compiled and executed after the test steps of the test cases in all the test databases are associated.
7. The method for testing faults based on hardware-in-the-loop simulation of claim 6, and further comprising the steps of generating an empty code interface and inputting the empty code interface into the test database to enable the test case to be associated with the empty code interface if the test step of the test case in the test database does not correspond to the fault injection control code in the process of associating the test step of the test case in the test database with the fault injection control code, notifying a developer of writing implementation codes of the empty code interface, and then regenerating the test case file.
8. The fault testing method based on hardware-in-the-loop simulation according to claim 7, wherein the test code is executed on the HIL rack to generate a test result, comprising the steps of: and executing test codes on the HIL rack through a DevOps scheduling method to generate a test result.
9. The method for testing faults based on hardware-in-the-loop simulation according to any one of claims 1 to 8, wherein the test data information further comprises a hardware frame, and the hardware frame is information of a brake of the electric automobile to be tested.
10. A fault testing system based on hardware-in-the-loop simulation, which is used for realizing the fault testing method based on hardware-in-loop simulation as claimed in any one of claims 1 to 9, and comprises the following modules connected in sequence: The test data input module is used for inputting test data information into the HIL rack and storing the test data information into the test database, wherein the test data information comprises test requirements, a software framework and HIL rack information; The test case module is used for analyzing the test requirement into a plurality of functional modules, wherein each functional module comprises one or more test items, matching the test items with the injection faults of the HIL rack, generating test cases and storing the test cases in the test database, and the test cases comprise one or more test steps; The test code generation module is used for carrying out modularized packaging on the fault injection control codes according to the HIL rack information and the software framework, and storing the modularized packaged fault injection control codes into a test database by using a file format; And the test code execution module is used for executing the test code on the HIL rack and generating a test result.

Description

Fault testing method and system based on hardware-in-loop simulation Technical Field The invention relates to the technical field of hardware-in-loop simulation, in particular to a fault test method and system based on hardware-in-loop simulation. Background The HIL (Hardware-in-the-Loop) is a technology for running simulation through a real-time processor, and an HIL rack (i.e. an HIL test rack) is combined with a precision control system through a physical structure support to realize an experimental device for verifying the functional performance of equipment or products, and a real electric control unit is connected with a virtual environment to perform closed-Loop test. The method has the advantages that virtual and real combination is realized, a real controller (such as an ECU) is connected into a virtual vehicle model to simulate various working conditions, safety and high efficiency are realized, a dangerous scene (such as sensor failure) can be repeatedly tested, and the method is widely applied to the fields of automobile electronics, aerospace, industrial equipment testing and the like. In the prior art, a brake product acquires HIL rack test from test requirements, and needs to manually decompose requirements, design test cases, write case test codes and the like, so that the whole flow time period is long. Therefore, the automatic test device has the problems of low automation degree, low test efficiency and the like. Disclosure of Invention In order to overcome the defects of the prior art, the invention provides a fault test method and system based on hardware-in-loop simulation, which solve the problems of low automation degree, low test efficiency and the like in the prior art. The technical scheme for solving the technical problems is as follows: a fault test method based on hardware-in-the-loop simulation comprises the following steps: Inputting test data information into the HIL rack and storing the test data information into a test database, wherein the test data information comprises test requirements, a software framework and HIL rack information; Analyzing the test requirement into a plurality of functional modules, wherein each functional module comprises one or more test items, matching the test items with the injection faults of the HIL rack, generating test cases and storing the test cases in a test database, and the test cases comprise one or more test steps; According to HIL rack information and a software framework, carrying out modularized packaging on the fault injection control codes, and storing the modularized packaged fault injection control codes into a test database by using a file format; and executing the test code on the HIL rack to generate a test result. The beneficial effects of the invention are as follows: According to the invention, the test requirement of the product is analyzed into a plurality of functional modules, each functional module comprises one or more test items, the test requirement, the software framework and the HIL rack information are automatically matched with the injection faults of the HIL rack, the test cases are automatically generated, then the test codes are generated, the test codes are executed, the full-closed loop automatic test of the fault injection HIL rack is completed, the automation degree is high, the test case manufacturing time is greatly shortened, and the test cases are combined with the modularized fault injection control codes to generate the test codes which can be directly operated, so that the labor investment for developing the test case codes is greatly reduced. On the basis of the technical scheme, the invention can be improved as follows. As a preferred technical solution, the analyzing the test requirement into a plurality of functional modules, each functional module including one or more test items, includes the following steps: and according to different test case code templates in the test database, disassembling the test requirements into independent test items. The beneficial effects of adopting the above preferable technical scheme are that: The test case code template is used for functionally analyzing the test requirement into a plurality of functional modules, and the functional modules comprise a plurality of test items, so that the efficiency is improved by 80% compared with the traditional manual decomposition requirement. As a preferable technical scheme, according to different test case code templates in a test database, the test requirements are disassembled into independent test items, and the method comprises the following steps: Analyzing the test requirement into a test case keyword by a finite state method; searching a test case code template in a test database through the test case keywords; And filling keyword information in the test case code template to generate a test case. The beneficial effects of adopting the above preferable technical scheme are that: the keyword retrieval has high