CN-121979732-A - Test instruction generation method, device, equipment and storage medium

CN121979732ACN 121979732 ACN121979732 ACN 121979732ACN-121979732-A

Abstract

The application provides a test instruction generation method, a device, equipment and a storage medium, belonging to the field of testing, wherein the method comprises the steps of obtaining a test request and instruction parameter modification information, wherein the instruction parameter modification information is generated based on parameter updating of a chip to be tested; selecting an instruction test case from a preset instruction test case type library according to the test request, determining test instruction parameter constraint information according to the test request, and performing test parameter adjustment on the instruction test case according to the test instruction parameter constraint information and the instruction parameter modification information to obtain a target instruction test case. According to the method and the device for testing the command parameters, the test parameter constraint information and the command parameter modification information are determined through the test request, and the command test case is subjected to test parameter adjustment, so that the target command test case meeting the requirements can be accurately obtained, the accuracy of the command test case is greatly improved, and the flexibility and the comprehensiveness of the configuration of the command test case are improved.

Inventors

WANG ANHUI
Ge Runlin
DING JIANING

Assignees

北京算能科技有限公司

Dates

Publication Date: 20260505
Application Date: 20251231

Claims (10)

1. A test instruction generation method, comprising: Acquiring a test request and instruction parameter modification information, wherein the instruction parameter modification information is generated based on parameter updating of a chip to be tested; selecting an instruction test case from a preset instruction test case type library according to the test request; Determining test instruction parameter constraint information according to the test request; and according to the test instruction parameter constraint information and the instruction parameter modification information, carrying out test parameter adjustment on the instruction test case to obtain a target instruction test case.
2. The method for generating test instructions according to claim 1, wherein said determining test instruction parameter constraint information according to said test request comprises: Analyzing the test request to obtain parameter definition information for indicating the generation of a test instruction; Acquiring a mapping relation table between preset test instruction parameter constraint information and parameter definition information, and inquiring test instruction parameter constraint information matched with the parameter definition information from the mapping relation table; the test instruction parameter constraint information comprises test case generation mode constraint, compatibility constraint, calculation storage constraint, address constraint and parameter constraint.
3. The test instruction generation method according to claim 1, wherein acquiring instruction parameter modification information includes: acquiring parameter updating information of the chip to be tested, and analyzing the parameter updating information to obtain parameter changing type information; and matching corresponding instruction parameter modification information from a preset instruction parameter modification information base based on the parameter change category information.
4. The method for generating test instructions according to claim 1, wherein selecting an instruction test case from a preset instruction test case type library according to the test request comprises: determining a test instruction type according to the test request; and selecting an instruction test from the preset instruction test case type library according to the test instruction type to obtain the instruction test case.
5. The method for generating test instructions according to claim 1, wherein said performing test parameter adjustment on said instruction test case according to said test instruction parameter constraint information and said instruction parameter modification information to obtain a target instruction test case comprises: Modifying the test instruction parameter constraint information according to the instruction parameter modification information to obtain target test instruction parameter constraint information; and carrying out test parameter adjustment on the instruction test case according to the target test instruction parameter constraint information to obtain the target instruction test case.
6. The method for generating test instructions according to claim 5, wherein said performing test parameter adjustment on said instruction test case according to said test instruction parameter constraint information and said instruction parameter modification information to obtain a target instruction test case comprises: According to the test instruction parameter constraint information and the instruction parameter modification information, carrying out multiple test parameter adjustment on the instruction test cases to obtain multiple candidate instruction test cases; And splicing the candidate instruction test cases to obtain a target instruction test case.
7. The test instruction generation method of any of claims 1-6, wherein the method further comprises: Acquiring a parameter value range of the target instruction test case, and acquiring a parameter value range required by the test of the chip to be tested; Determining the coverage rate of the test parameters according to the parameter value range and the parameter value range required by the test; And if the coverage rate of the test parameters is smaller than or equal to the coverage rate of the preset test parameters, outputting an uncovered parameter value range.
8. The test instruction generating device is characterized by comprising an acquisition module, a selection module, a determination module and a generation module, wherein: the acquisition module is used for acquiring a test request and instruction parameter modification information, wherein the instruction parameter modification information is generated based on parameter updating of a chip to be tested; The selection module is used for selecting an instruction test case from a preset instruction test case type library according to the test request, wherein the preset instruction test case type library is an instruction test case library established in advance based on a plurality of instruction test case types; The determining module is used for determining constraint information of test instruction parameters according to the test request; the generating module is used for carrying out test parameter adjustment on the instruction test case according to the test instruction parameter constraint information and the instruction parameter modification information to obtain a target instruction test case.
9. A computer device comprising a processor, a memory, and a computer program stored on the memory and executable by the processor, wherein the computer program when executed by the processor implements the steps of the test instruction generation method of any of claims 1 to 7.
10. A computer readable storage medium, characterized in that the computer readable storage medium has stored thereon a computer program, wherein the computer program, when executed by a processor, implements the steps of the test instruction generation method according to any of claims 1 to 7.

Description

Test instruction generation method, device, equipment and storage medium Technical Field The present application relates to the field of testing technologies, and in particular, to a method, an apparatus, a device, and a storage medium for generating a test instruction. Background With the advancement of technology, large language models such as GPT-4 and DeepSeek are issued successively, the power demand of equipment is exponentially increased correspondingly to the training and reasoning of the large language models, compared with the traditional CPU and GPU, TPU (Tensor Processing Unit, tensor processor) or NPU (Neural network Processing Unit, neural network processor) and various AI special acceleration chips can provide order-of-magnitude advantages in terms of power, bandwidth and energy consumption ratio, and accordingly, the testing of the hardware function correctness and performance limit of the chip is also a very important circle, and the chip function verification is mainly aimed at ensuring the correct function of the verified chip. Currently, verification methods include EDA verification, formal verification, verification of combination, FPGA verification, and the like. Chip verification often supports hundreds of custom instructions, tens of tensor data formats and various mixed precision modes, so a large number of test cases are needed for verification test, wherein the test can be divided into random test and directional test according to different generation modes, the random test has high repeatability, and some scenes can not be covered completely, the directional test also needs to take huge time cost and test point omission easily occurs, and the test data is insufficient in the current chip test, so that the test of the chip is inaccurate and incomplete. Therefore, how to generate a large number of test instructions for chip testing is a current urgent problem to be solved. Disclosure of Invention The application mainly aims to provide a test instruction generation method, a device, equipment and a storage medium, aiming at improving the coverage rate and accuracy of the generated test instruction and further improving the efficiency and accuracy of a chip. In a first aspect, the present application provides a test instruction generation method, including the steps of: Acquiring a test request and instruction parameter modification information, wherein the instruction parameter modification information is generated based on parameter updating of a chip to be tested; selecting an instruction test case from a preset instruction test case type library according to the test request; Determining test instruction parameter constraint information according to the test request; and according to the test instruction parameter constraint information and the instruction parameter modification information, carrying out test parameter adjustment on the instruction test case to obtain a target instruction test case. In a second aspect, the present application further provides a test instruction generating device, where the test instruction generating device includes an obtaining module, a selecting module, a determining module, and a generating module, where: the acquisition module is used for acquiring a test request and instruction parameter modification information, wherein the instruction parameter modification information is generated based on parameter updating of a chip to be tested; The selection module is used for selecting an instruction test case from a preset instruction test case type library according to the test request, wherein the preset instruction test case type library is an instruction test case library established in advance based on a plurality of instruction test case types; The determining module is used for determining constraint information of test instruction parameters according to the test request; the generating module is used for carrying out test parameter adjustment on the instruction test case according to the test instruction parameter constraint information and the instruction parameter modification information to obtain a target instruction test case. In a third aspect, the present application also provides a computer device comprising a processor, a memory, and a computer program stored on the memory and executable by the processor, wherein the computer program when executed by the processor implements the steps of the test instruction generation method as described above. In a fourth aspect, the present application also provides a computer readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the steps of a test instruction generation method as described above. The application provides a test instruction generation method, a device, equipment and a storage medium, wherein the method acquires a test request and instruction parameter modification information, wherein the instru