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CN-121979808-A - Memory allocation method, memory allocation device, chip, electronic equipment and storage medium

CN121979808ACN 121979808 ACN121979808 ACN 121979808ACN-121979808-A

Abstract

The application provides a memory allocation method, a device, a chip, electronic equipment and a storage medium, wherein the memory allocation method comprises the steps of setting a local first memory for a plurality of computing modules, allocating first buffer areas for the first memories corresponding to the computing modules respectively, allocating a plurality of first virtual addresses for the first buffer areas, wherein the first virtual addresses corresponding to the computing modules are continuous, the first virtual addresses comprise computing module identifiers and address offset in the first buffer areas, and executing data access operation based on the first virtual addresses and the second memories of the first memories of the computing modules. According to the application, the data access efficiency of the computing module can be improved.

Inventors

  • Zhao Recong

Assignees

  • 上海东方算芯科技有限公司

Dates

Publication Date
20260505
Application Date
20260403

Claims (12)

  1. 1. The memory allocation method is characterized by comprising the following steps: Setting a local first memory for a plurality of computing modules, wherein each computing module comprises a first memory and a second memory; Allocating first buffer areas to the first memories respectively corresponding to the plurality of computing modules, wherein each first memory corresponds to each first buffer area one by one; allocating a plurality of first virtual addresses to each first buffer zone, wherein the plurality of first virtual addresses corresponding to one computing module are continuous, and the first virtual addresses comprise computing module identifications and address offsets in the first buffer zone; And executing data access operation based on the first virtual address of the first memory and the second memory of the computing module.
  2. 2. The method of claim 1, wherein the method is applied to a chip, the chip comprises a network on chip and a plurality of computing modules, each computing module is interconnected through the network on chip, and the same virtual address space is shared among each computing module.
  3. 3. The method according to claim 2, wherein the method further comprises: acquiring a writing virtual address of a first computing module carried by a first data access request, a reading virtual address of a second computing module and requested first target data, wherein the writing virtual address is a first virtual address used for writing the first target data, and the reading virtual address is a first virtual address used for reading the first target data; reading the first target data from the read virtual address if the first computing module identification of the write virtual address is different from the second computing module identification of the read virtual address; And transmitting the first target data to the first computing module through the network-on-chip, and storing the first target data to the writing virtual address of the first computing module.
  4. 4. The method of claim 1, wherein allocating a first buffer to the first memories to which the plurality of computing modules respectively correspond comprises: determining a first data volume of the first buffer zone according to a first communication task; Determining, for each of the computing modules, a contiguous physical memory space of a first amount of data from free physical pages of a first memory of the computing module; The contiguous physical storage space of the first data amount is taken as the first buffer zone of the first memory.
  5. 5. The method of claim 4, wherein after said treating the contiguous physical storage space of the first data amount as the first buffer of the first memory, the method further comprises: Responsive to receiving a second communication task, determining a second amount of data in accordance with the second communication task; Responsive to the second amount of data being greater than the first amount of data and not including data in the first buffer, withdrawing the first buffer; determining, for each of the computing modules, a contiguous physical memory space of a second amount of data from free physical pages of a first memory of the computing module; and taking the continuous physical storage space of the second data volume as the updated first buffer area.
  6. 6. The method of claim 1, wherein the first virtual address is comprised of a high-order field and a low-order field; the allocating a plurality of first virtual addresses for each of the first buffer areas includes: the following processing is performed for each of the first buffers: The computing module identification of the computing module where the first buffer is located is used as the high-order field of each first virtual address; Determining a plurality of address offsets according to the upper limit of the data capacity of the first buffer zone, and taking the address offsets as the low-order fields of the first virtual address respectively; and combining each high-order address with the low-order address to obtain the plurality of first virtual addresses, wherein the coding modes of low-order fields of the plurality of first virtual addresses of the plurality of computing modules are the same.
  7. 7. The method of claim 1, wherein performing a data access operation based on a first virtual address of a first memory and a second memory of the computing module comprises: For each of the computing modules, performing the following: Acquiring a target virtual address carried by a second data access request and second target data requested, wherein the target virtual address comprises a target computing module identifier and a target address offset; Determining a target physical address in the first memory based on the target address offset if the target computing module identification is the same as a computing module identification in a first virtual address of the computing module identification; And establishing a second transmission path between the physical space pointed by the target physical address and the second memory, and transmitting second target data between the first memory and the second memory based on the second transmission path.
  8. 8. The method of claim 7, wherein the first memory is a dynamic random access memory and the second memory is a static random access memory.
  9. 9. A memory allocation apparatus, the apparatus comprising: a buffer allocation module for setting a local first memory for a plurality of computing modules, wherein each computing module comprises a first memory and a second memory; allocating first buffer areas to the first memories respectively corresponding to the plurality of computing modules, wherein each first memory corresponds to each first buffer area one by one; an address allocation module, configured to allocate a plurality of first virtual addresses to each of the first buffers, where the plurality of first virtual addresses corresponding to one of the computing modules are consecutive, and the first virtual addresses include a computing module identifier and an address offset in the first buffer; and the data access module is used for executing data access operation based on the first virtual address of the first memory and the second memory of the computing module.
  10. 10. A chip, wherein the chip comprises a plurality of computing modules and a network on chip, each computing module comprises a first memory and a second memory, the first memory is a dynamic random access memory, and the second memory is a static random access memory; the chip is used for realizing the memory allocation method according to any one of claims 1 to 8.
  11. 11. An electronic device, the electronic device comprising: a memory for storing computer executable instructions or computer programs; A processor for implementing the memory allocation method of any one of claims 1 to 8 when executing computer executable instructions or computer programs stored in said memory.
  12. 12. A computer readable storage medium storing computer executable instructions or a computer program, wherein the computer executable instructions or the computer program when executed by a processor implement the memory allocation method of any one of claims 1 to 8.

Description

Memory allocation method, memory allocation device, chip, electronic equipment and storage medium Technical Field The present application relates to network-on-chip technology, and in particular, to a memory allocation method, apparatus, chip, electronic device, and storage medium. Background In a multi-processing node or multi-computing module (computing Tile) architecture, frequent data interactions and co-processing between the computing modules are often required. Under a conventional memory allocation and mapping mechanism, a physical address cross-module rotation (Interleaving) strategy is generally adopted to allocate global physical memory. Under this mechanism, the physical memory pages of the intermediate buffer required for a single communication task are discretely distributed in Dynamic Random Access Memory (DRAM) to which a plurality of different computing modules are connected. When a single computing module is performing data processing and initiating load or store operations to the intermediate buffer, its access requests and data often need to be frequently processed across a network on chip (NoC) by a dynamic random access memory node that is routed to other computing modules at a remote location. Because the physical addresses of the intermediate buffers are discretely distributed, a large amount of cross-module data transmission can increase the communication load of the network on chip, and introduce additional multi-hop routing node circulation time and remote access delay. In addition, access delay caused by accessing remote storage across a network on chip has uncertainty, so that the communication pipeline in charge of data flow in the computing module is easy to wait or interrupt in the execution process, global data throughput and storage bandwidth utilization rate are further affected when a plurality of modules work cooperatively, and data access (data storage or data loading) efficiency of the computing module is reduced. Disclosure of Invention The embodiment of the application provides a memory allocation method, a memory allocation device, a chip, electronic equipment and a storage medium, which can improve the data access efficiency of a computing module. The technical scheme of the embodiment of the application is realized as follows: the embodiment of the application provides a memory allocation method, which comprises the following steps: Setting a local first memory for a plurality of computing modules, wherein each computing module comprises a first memory and a second memory; Allocating first buffer areas to the first memories respectively corresponding to the plurality of computing modules, wherein each first memory corresponds to each first buffer area one by one; allocating a plurality of first virtual addresses to each first buffer zone, wherein the plurality of first virtual addresses corresponding to one computing module are continuous, and the first virtual addresses comprise computing module identifications and address offsets in the first buffer zone; And executing data access operation based on the first virtual address of the first memory and the second memory of the computing module. The embodiment of the application provides a memory allocation device, which comprises: a buffer allocation module for setting a local first memory for a plurality of computing modules, wherein each computing module comprises a first memory and a second memory; allocating first buffer areas to the first memories respectively corresponding to the plurality of computing modules, wherein each first memory corresponds to each first buffer area one by one; an address allocation module, configured to allocate a plurality of first virtual addresses to each of the first buffers, where the plurality of first virtual addresses corresponding to one of the computing modules are consecutive, and the first virtual addresses include a computing module identifier and an address offset in the first buffer; and the data access module is used for executing data access operation based on the first virtual address of the first memory and the second memory of the computing module. The embodiment of the application provides a chip, which comprises a plurality of computing modules and a network on chip, wherein each computing module comprises a first memory and a second memory, the first memory is a dynamic random access memory, and the second memory is a static random access memory; the chip is used for realizing the memory allocation method according to the embodiment of the application. An embodiment of the present application provides an electronic device, including: a memory for storing computer executable instructions or computer programs; and the processor is used for realizing the memory allocation method provided by the embodiment of the application when executing the computer executable instructions or the computer programs stored in the memory. The embodiment of the application provides a