CN-121979809-A - Data processing method, multi-core heterogeneous system and computer readable storage medium

CN121979809ACN 121979809 ACN121979809 ACN 121979809ACN-121979809-A

Abstract

The application discloses a data processing method, a multi-core heterogeneous system and a computer readable storage medium, which belong to the technical field of data processing, wherein the method comprises the steps of allocating physical storage space based on a predefined physical address boundary in a hardware system initialization stage, wherein the physical storage space comprises a shared space; and in the starting stage of the operating system, acquiring an address mapping relation, wherein the address mapping relation comprises a target mapping relation, and under the condition that the operating system runs, the storage management module is triggered to execute target operation based on the address mapping relation, the configuration data and a virtual address corresponding to the instruction, wherein the target operation is read operation or write operation. The calculation amount of the processor is greatly reduced, and the time consumption for reading and writing data is reduced as a whole.

Inventors

LAI JINGZHOU
ZHANG BIN
XIONG QINWEI

Assignees

深圳市紫光同创电子股份有限公司

Dates

Publication Date: 20260505
Application Date: 20251204

Claims (10)

1. A data processing method, applied to a processor of a multi-core heterogeneous system, the multi-core heterogeneous system further comprising a storage management module, the method comprising: In the initialization stage of the hardware system, physical storage space is allocated based on a predefined physical address boundary, and the physical storage space comprises a shared space; in the initialization stage of the hardware system, writing the predefined configuration data corresponding to the shared space into a configuration register of the storage management module and latching the configuration register, wherein the configuration data comprises an access control strategy and storage attributes; In the starting stage of an operating system, an address mapping relation is obtained, wherein the address mapping relation comprises a target mapping relation, and the target mapping relation is the corresponding relation between a physical address and a virtual address of the shared space; under the condition that an operating system runs, an instruction based on a target operation triggers the storage management module to execute the target operation based on the address mapping relation, the configuration data and a virtual address corresponding to the instruction, wherein the target operation is a read operation or a write operation.
2. The method of claim 1, wherein the processor includes a plurality of processing cores, the physical memory space further includes a private space of each of the processing cores, and the acquiring the address mapping relationship during the operating system boot phase includes: In an operating system starting stage, determining a physical address of the shared space and a physical address of a private space of each processing core based on a device tree; And establishing an address mapping relation based on the physical address of the shared space and the physical address of the private space of each processing core.
3. The method of claim 2, wherein said determining the physical address of the shared space and the physical address of the private space of each of the processing cores based on the device tree during the operating system boot phase comprises: in the starting stage of an operating system, judging whether the equipment tree is matched with information stored in each register of the storage management module or not, and judging whether the equipment tree is matched with the physical address boundary or not; If the device tree matches the information stored by the respective registers of the storage management module and matches the physical address boundaries, determining a physical address of the shared space and a physical address of a private space of each of the processing cores based on the device tree.
4. The method of claim 2, wherein the target mapping relationship comprises a plurality of sub-mapping relationships, each of the sub-mapping relationships being a correspondence relationship between a physical address of the shared space and a virtual address of one of the processing cores.
5. The method of claim 2, wherein the device tree is predefined based on the physical address boundary.
6. A multi-core heterogeneous system, comprising: a storage management module and a processor for performing the data processing method of any of claims 1-5.
7. The multi-core heterogeneous system of claim 6, wherein, The storage management module comprises a memory management unit, a global memory protection unit, a cache controller and a storage controller, wherein a configuration register of the global memory protection unit is used for storing the configuration data; the memory management unit is used for determining a target physical address corresponding to the instruction based on the address mapping relation and a target virtual address corresponding to the instruction, the global memory protection unit is used for determining access authority of the target physical address based on the target physical address and the access control strategy, the cache controller is used for determining a cache strategy based on a storage attribute of the target physical address under the condition that the target physical address has the access authority, and the storage controller is used for executing target operation based on the cache strategy and the target physical address.
8. The multi-core heterogeneous system of claim 6, wherein, The processor comprises a plurality of processing cores, at least two processing cores comprise cache modules, and the storage attribute of the shared space comprises a cache policy corresponding to each cache module.
9. A computer readable storage medium, characterized in that the computer readable storage medium has stored therein a program code, which is callable by a processor for executing the method according to any one of claims 1-5.
10. A computer program product comprising computer programs/instructions which, when executed by a processor, implement the method of any of claims 1-5.

Description

Data processing method, multi-core heterogeneous system and computer readable storage medium Technical Field The present application relates to the field of data processing technology, and more particularly, to a data processing method, a multi-core heterogeneous system, and a computer readable storage medium. Background In an asymmetric (ASYMMETRIC MULTI-Processing, AMP) multi-core heterogeneous system, a central Processing unit (Central Processing Unit, CPU) includes multiple Processing cores, there is no shared operating system schedule between the different Processing cores, and cache inconsistencies may occur if some Processing core modifies the shared memory while old data remains in the caches of other Processing cores. Existing methods for implementing inter-core communication for asymmetric multi-core heterogeneous systems are time consuming. Disclosure of Invention The application provides a data processing method, a multi-core heterogeneous system and a computer readable storage medium, so as to improve the defects. In a first aspect, the application provides a data processing method, which is applied to a processor of a multi-core heterogeneous system, wherein the multi-core heterogeneous system further comprises a storage management module, the method comprises the steps of distributing a physical storage space based on a predefined physical address boundary in a hardware system initialization stage, enabling predefined configuration data corresponding to the shared space to be written into a configuration register of the storage management module and latching the configuration register in the hardware system initialization stage, enabling the configuration data to comprise an access control strategy and a storage attribute, obtaining an address mapping relation in an operating system starting stage, enabling the address mapping relation to comprise a target mapping relation, enabling the target mapping relation to be a corresponding relation between a physical address and a virtual address of the shared space, and enabling the storage management module to execute a target operation based on the address mapping relation, the configuration data and the virtual address corresponding to the command based on an instruction of the target operation under the condition that the operating system runs. Optionally, for one possible implementation manner, the processor includes a plurality of processing cores, the physical storage space further includes private spaces of the respective processing cores, and the acquiring an address mapping relationship in the operating system startup phase includes determining, based on a device tree, a physical address of the shared space and a physical address of a private space of each processing core in the operating system startup phase, and establishing an address mapping relationship based on the physical address of the shared space and the physical address of the private space of each processing core. Optionally, for a possible implementation manner, the step of determining the physical address of the shared space and the physical address of the private space of each processing core based on the device tree in the operating system startup stage includes determining whether the device tree matches information stored in each register of the storage management module and determining whether the device tree matches the physical address boundary in the operating system startup stage, and if the device tree matches information stored in each register of the storage management module and matches the physical address boundary, determining the physical address of the shared space and the physical address of the private space of each processing core based on the device tree. Optionally, for a possible implementation manner, the target mapping relationship includes a plurality of sub-mapping relationships, and each sub-mapping relationship is a corresponding relationship between a physical address of the shared space and a virtual address of one of the processing cores. Optionally, for a possible implementation, the device tree is predefined based on the physical address boundary. In a second aspect, the application also provides a multi-core heterogeneous system, which comprises a storage management module and a processor, wherein the processor is used for executing the data processing method in the first aspect. Optionally, for one possible implementation manner, the storage management module includes a memory management unit, a global memory protection unit, a cache controller and a storage controller, where a configuration register of the global memory protection unit is used to store the configuration data, the memory management unit is used to determine a target physical address corresponding to the instruction based on the address mapping relationship and a target virtual address corresponding to the instruction, the global memory protection unit is used to determine