Search

CN-121979811-A - Data access method and device, electronic equipment and storage medium

CN121979811ACN 121979811 ACN121979811 ACN 121979811ACN-121979811-A

Abstract

The disclosure provides a data access method, a device, an electronic device and a storage medium, wherein the method comprises the steps of determining at least one memory to be processed; the method comprises the steps of obtaining data access information corresponding to each memory to be processed, determining an array memory from at least one memory to be processed according to the data access information, carrying out cache utilization rate analysis on the array memory, determining a rearrangement array according to analysis results, determining conversion parameters according to the data access information of the rearrangement array, converting access operation of the rearrangement array by utilizing the conversion parameters, and carrying out data access by utilizing the converted access operation.

Inventors

  • GAO FENG
  • LU SHIWEI

Assignees

  • 飞腾信息技术有限公司

Dates

Publication Date
20260505
Application Date
20251219

Claims (12)

  1. 1. A method of data access, the method comprising: Determining at least one memory to be processed; acquiring data access information corresponding to each memory to be processed, and determining an array memory from the at least one memory to be processed according to the data access information; performing cache utilization rate analysis on the array memory, and determining a rearranged array according to an analysis result; Determining a conversion parameter according to the data access information of the rearranged array, and converting the access operation of the rearranged array by using the conversion parameter; and performing data access by using the converted access operation.
  2. 2. The method of claim 1, wherein the array access information comprises a function of an access array, an access operation of the access array, an access data type of the access operation, the access data type characterizing a data length of the access; The data access information corresponding to each memory to be processed is obtained, wherein the data access information comprises the array access information of the memory to be processed, which is tracked by a DU chain, for the memory to be processed; determining an array memory from the at least one memory to be processed according to the data access information, including: and determining the memory to be processed as the array memory or the non-array memory according to the access data type of each access operation, wherein if the access data types of all the access operations on the memory to be processed are consistent, the memory to be processed is determined as the array memory.
  3. 3. The method of claim 2, wherein if the memory to be processed is an array memory, the obtaining the data access information corresponding to each memory to be processed further comprises: determining the function and the circulation type of each access operation, wherein the circulation type represents that the access operation belongs to the inside or the outside of the circulation; And classifying all the access operations according to the function and the circulation type of each access operation to obtain access operations in the circulation and/or access operations outside the circulation.
  4. 4. The method of claim 1, wherein performing cache utilization analysis on the array memory, determining a reorder array based on the analysis result, comprises: Determining each cycle in which an access operation for accessing the array memory is located; determining a step length of the loop and access offset information of the array memory for each loop, wherein the access offset information comprises at least one access offset; Determining the cache utilization rate in the existing circulation in the array according to the step length and the access offset information; if the cache utilization rate is lower than a threshold value, determining that the array memory is a rearrangement array; Wherein determining, according to the step size and the access offset information, a cache utilization rate in a presence cycle in the array includes: Determining a remainder result corresponding to each access offset according to each access offset and the step length; And determining the number of the remainder results which are different from each other, and determining the cache utilization rate in the existence cycle in the array according to the number and the step length.
  5. 5. The method of claim 1, wherein determining conversion parameters from the rearranged array of data access information comprises: Determining each cycle in which an access operation for accessing the rearranged array is located and a step length of each cycle; Determining a first conversion parameter according to the least common multiple of the step length of each cycle; determining a data type length of an access operation for accessing the reorder array and a size parameter in an allocation operation of the reorder array; Determining an array length according to the data type length and the size parameter; determining a second conversion parameter according to the array length and the first conversion parameter; the first conversion parameter and the second conversion parameter are used for converting the access operation of the rearrangement array.
  6. 6. The method of claim 1, wherein converting access operations of the reordered array using the conversion parameters comprises: for each function accessing the reordered array, performing a transformation of an out-of-loop access operation and/or a transformation of an in-loop access operation using the transformation parameters.
  7. 7. The method of claim 6, wherein performing the conversion of the out-of-loop access operation using the conversion parameters comprises: determining the data type length and the access offset of the access operation for accessing the rearranged array; Determining an array subscript corresponding to the access operation according to the access offset and the data type length; determining a new access offset of the access operation according to the array subscript, the data type length and the conversion parameter; And performing access operation by using the new access offset.
  8. 8. The method of claim 6, wherein if the step sizes of the loops accessing the reordered array are different, performing the conversion of the access operation within the loops using the conversion parameters comprises: determining a round robin induction variable, a data type length and an access offset of an access operation for accessing the reordered array; according to the data type length and the access offset of the access operation, calculating an array subscript corresponding to the access operation; Determining a new access offset of the access operation according to the array subscript, the cycle induction variable, the data type length and the conversion parameter; And performing access operation by using the new access offset.
  9. 9. The method of claim 6, wherein performing the conversion of the access operation within the loop using the conversion parameter if the step size of the loop accessing the reordered array is the same, comprises: determining a round robin induction variable, a data type length and an access offset of an access operation for accessing the reordered array; According to the initial value of the cycle inductive variable and the step length of the cycle, constructing a new inductive variable, and adding an increment operation for the new inductive variable; Determining an array subscript corresponding to the access operation according to the access offset and the data type length; Determining a new access offset of the access operation according to the new induction variable, the array subscript, the data type length and the conversion parameter; And performing access operation by using the new access offset.
  10. 10. A data access device, the device comprising: the acquisition module is used for determining at least one memory to be processed based on memory screening conditions; The first processing module is used for acquiring data access information corresponding to each memory to be processed and determining an array memory from the at least one memory to be processed according to the data access information; the second processing module is used for carrying out cache utilization analysis on the array memory and determining a rearrangement array according to an analysis result; The third processing module is used for determining conversion parameters according to the data access information of the rearranged array, and converting the access operation of the rearranged array by utilizing the conversion parameters; and the fourth processing module is used for accessing the data by using the converted access operation.
  11. 11. An electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, characterized in that the processor implements the steps of the method of any one of claims 1 to 9 when the program is executed by the processor.
  12. 12. A computer readable storage medium, on which a computer program is stored, characterized in that the computer program, when being executed by a processor, implements the steps of the method according to any one of claims 1 to 9.

Description

Data access method and device, electronic equipment and storage medium Technical Field The disclosure relates to the field of computer technology, and in particular, to a data access method, a data access device, electronic equipment and a storage medium. Background Both software and hardware performance can impact computational performance, which is particularly pronounced in some special applications. The cache is copied as a part of the memory, and has a faster access speed than the memory, but due to the limited storage capacity, the data in the cache is frequently replaced by other data in the memory. The data in the cache is typically accessed in units of lines, typically 64 bytes. In practice, not all of the 64 bytes of data of a cache line are accessed. When the processor executes the memory access operation, the whole data with the access address is loaded into the cache, and if the data loaded into the cache is not all accessed before being replaced, the use efficiency of the data to the cache is lower. An example of arrangement of the data D is provided below. The data D is stored in a continuous memory in the form of array, and the size of the data D is nM, m is larger, n is smaller, nM exceeds the total cache size. For ease of illustration, it is assumed that n data occupies exactly one cache line, and the arrangement is shown in FIG. 1. There are functions 1,2, functionN, one cycle in each Function (Function) to access data D, the access rules are as follows: The loop in Function1 accesses data D m times with an offset=0, a step size stride=n, with access rules field [0], field [ n ], field [2n ], field [ (m-1) n ]. The loop in Function2 accesses data D m times with an offset=1, a step size stride=n, with access rules of field [1], field [ n+1 ], field [ 2n+1 ], field [ (m-1) n+1 ]. The loop in FunctionN accesses data m times with offset=n-1, stride=n, with access rules field [ n-1], field [2n-1], field [ 3n+1 ], field [ m ]n - 1]。 The access laws of Function1, function2, functionN are shown in fig. 2. Program P was executed in the order of Function1, function2, and FunctionN. Loop i (0≤i < m) accesses will field [ n ] when Function1 is executedI ] is loaded into the cache, i.e. field ni]、field[ni+1]、...、field[nI+n-1], but only field [ n ] is usedI ]; because data D is large, the cache is not sufficient to hold all data, assuming the total number of cache lines is k lines, the cache is exhausted by data D when i=k accesses, if the cache adopts LRU (LEAST RECENTLY Used ) replacement policy, the number field [0], field [1], field [ n-1] loaded into the cache for the 0 th access will be by field [ n ]k]、field[nk+1]、...、field[nK+n-1] and so on k+i accesses will replace the data loaded into the cache the ith time. The buffer status at the kth access is shown in FIG. 3, when all buffers are occupied by data D, and the buffer status at the kth+1th access is shown in FIG. 4, according to LRU replacement rules, the buffer line where filled [0] is located is filled [ k ]N ] substitution. When program P begins to execute Function2, function2 reloads the entire line of data where field [1] is located into the cache when accessing field [1] because field [0], field [1],. The field [ n-1] has been replaced with the cache. Functions 3 to FunctionN behave similarly, and the utilization rate of the program P to the cache under the access model is only 1/n. Disclosure of Invention The present disclosure provides a data access method, apparatus, electronic device, and storage medium, so as to at least solve the above technical problems in the prior art. In a first aspect, an embodiment of the present disclosure provides a data access method, including: Determining at least one memory to be processed; acquiring data access information corresponding to each memory to be processed, and determining an array memory from the at least one memory to be processed according to the data access information; performing cache utilization rate analysis on the array memory, and determining a rearranged array according to an analysis result; Determining a conversion parameter according to the data access information of the rearranged array, and converting the access operation of the rearranged array by using the conversion parameter; and performing data access by using the converted access operation. In a second aspect, embodiments of the present disclosure provide a data access apparatus, the apparatus comprising: the acquisition module is used for determining at least one memory to be processed based on memory screening conditions; The first processing module is used for acquiring data access information corresponding to each memory to be processed and determining an array memory from the at least one memory to be processed according to the data access information; the second processing module is used for carrying out cache utilization analysis on the array memory and determining a rearrangement array according to an analysis