CN-121979817-A - Processing module, request processing method applied to processing module, chip and system

Abstract

The application discloses a processing module, a request processing method applied to the processing module, a chip and a system, and belongs to the field of chips. The processing module comprises a receiving module, a distributing module, a caching module and a data link module, wherein the caching module comprises at least two caching units, the receiving module is used for receiving at least one memory writing request, the distributing module is used for determining a first caching unit from at least two caching units according to a first memory writing request in the at least one memory writing request and sending the first memory writing request to the first caching unit, the first caching unit is used for caching the first memory writing request and sending the first memory writing request to the data link module, and the data link module is used for receiving the first memory writing request and processing the first memory writing request. The processing module improves the processing speed of the memory writing request through at least two cache units.

Inventors

• ZHU XIAOMING
• YI FENG

Assignees

• 海光信息技术股份有限公司

Dates

Publication Date

20260505

Application Date

20251225

Claims (19)

1. 1. The processing module is characterized by comprising a receiving module, a distributing module, a cache module and a data link module, wherein the cache module comprises at least two cache units; The receiving module is used for receiving at least one memory writing request, wherein the memory writing request is a request sent by ports for writing data into a memory, and the number of the ports is at least two; The distribution module is configured to determine, for a first memory write request in the at least one memory write request, a first cache unit from the at least two cache units, and send the first memory write request to the first cache unit; the first caching unit is configured to cache the first memory write request, and send the first memory write request to the data link module; The data link module is configured to receive the first memory write request, and process the first memory write request.
2. 2. The processing module of claim 1, wherein the processing module comprises a plurality of processing modules, The distribution module is configured to determine, for the first memory write request, the first cache unit from the at least two cache units according to a port that sends the first memory write request; the distribution module is configured to send the first memory write request to the first cache unit.
3. 3. The processing module of claim 2, wherein the first memory write request includes port information indicating a first port that sent the first memory write request; The distribution module is configured to determine, for the first memory write request, the first cache unit corresponding to the first port from the at least two cache units according to port information included in the first memory write request; the distribution module is configured to send the first memory write request to the first cache unit.
4. 4. A processing module according to any one of claims 1 to 3, wherein the first buffer unit includes a first buffer area for buffering request data of the first memory write request and a second buffer area for buffering write data of the first memory write request, the request data being data related to the first memory write request itself, the write data being data to be written into a memory by the first memory write request.
5. 5. The processing module of claim 4, wherein the processing module comprises a plurality of processing modules, The first buffer unit is configured to, when the first memory write request is allowed to be sent to the data link module, read request data of the first memory write request from the first buffer area, and read write data of the first memory write request from the second buffer area, so as to obtain a transaction layer packet corresponding to the first memory write request; The first buffer unit is configured to send a transaction layer packet corresponding to the first memory write request to the data link module; the data link module is configured to receive a transaction layer packet corresponding to the first memory write request, and process the first memory write request.
6. 6. The processing module of claim 5, wherein the processing module comprises a processing module, The first buffer unit is configured to read request data of the first memory write request from the first buffer area, where the request data of the first memory write request includes length indication information, where the length indication information is used to indicate a data length of the write data of the first memory write request; and the first cache unit is used for reading the write-in data of the first memory write-in request from the second cache area according to the length indication information.
7. 7. A process module according to any one of claims 1 to 6, A second cache unit of the at least two cache units is configured to cache a second memory write request of the at least one memory write request; the second buffer unit is configured to send the second memory write request to the data link module; wherein the first memory write request and the second memory write request are allowed to be sent in parallel to the data link module.
8. 8. A process module according to any one of claims 1 to 6, The data link module is further configured to determine, according to the first cache unit, a port for sending the first memory write request.
9. 9. The processing module according to any one of claims 1 to 6, wherein the cache module includes a data cache area and an address cache area; the data caching area is used for caching the at least one memory writing request; The address cache area is configured to cache address information of the at least one memory write request, where the address information of the memory write request is a cache address of the memory write request in the data cache area.
10. 10. The processing module of claim 9, wherein the processing module comprises a plurality of processing modules, The buffer module is configured to obtain address information of a third memory write request from the address buffer area when sending the third memory write request in the at least one memory write request to the data link module; and the cache module is used for acquiring the third memory write request from the data cache area according to the address information of the third memory write request.
11. 11. The processing module of claim 9, wherein the processing module comprises a plurality of processing modules, The address cache area is further configured to cache port information of the at least one memory write request, where the port information of the memory write request is used to indicate a port that sends the memory write request.
12. 12. The request processing method applied to the processing module is characterized in that the processing module comprises a receiving module, a distributing module, a cache module and a data link module, wherein the cache module comprises at least two cache units, and the method comprises the following steps: The receiving module receives at least one memory writing request, wherein the memory writing request is a request sent by ports for writing data into a memory, and the number of the ports is at least two; The distribution module determines a first cache unit from the at least two cache units for a first memory write request in the at least one memory write request, and sends the first memory write request to the first cache unit; The first caching unit caches the first memory writing request and sends the first memory writing request to the data link module; the data link module receives the first memory writing request and processes the first memory writing request.
13. 13. The method of claim 12, wherein the distributing module determining, for a first memory write request of the at least one memory write request, a first cache unit from the at least two cache units, the first memory write request to the first cache unit, comprises: the distribution module determines the first cache unit from the at least two cache units according to a port for sending the first memory write request aiming at the first memory write request; And the distribution module sends the first memory writing request to the first cache unit.
14. 14. The method of claim 13, wherein the first memory write request includes port information indicating a first port that sent the first memory write request; the distributing module determines, for the first memory write request, the first cache unit from the at least two cache units according to a port that sends the first memory write request, including: The distribution module determines, for the first memory write request, the first cache unit corresponding to the first port from the at least two cache units according to port information included in the first memory write request.
15. 15. The method according to any one of claims 12 to 14, wherein the first buffer unit includes a first buffer area for buffering request data of the first memory write request and a second buffer area for buffering write data of the first memory write request, the request data being data related to the first memory write request itself, the write data being data to be written into a memory by the first memory write request.
16. 16. The method of claim 15, wherein the first cache unit sending the first memory write request to the data link module comprises: Under the condition that the first memory writing request is allowed to be sent to the data link module, the first cache unit reads request data of the first memory writing request from the first cache area, reads writing data of the first memory writing request from the second cache area, and obtains a transaction layer packet corresponding to the first memory writing request; The first buffer unit sends a transaction layer packet corresponding to the first memory writing request to the data link module; The data link module receives the first memory write request, processes the first memory write request, and includes: and the data link module receives a transaction layer packet corresponding to the first memory writing request and processes the first memory writing request.
17. 17. The method of claim 16, wherein the first cache unit reading the request data of the first memory write request from the first cache region and the write data of the first memory write request from the second cache region comprises: The first cache unit reads request data of the first memory write request from the first cache area, wherein the request data of the first memory write request comprises length indication information, and the length indication information is used for indicating the data length of the write data of the first memory write request; And the first cache unit reads the write-in data of the first memory write-in request from the second cache area according to the length indication information.
18. 18. A data processing chip is characterized in that, The data processing chip is used for receiving at least one memory writing request, wherein the memory writing request is a request sent by ports for writing data into a memory, and the number of the ports is at least two; the data processing chip is further configured to buffer, for a first memory write request in the at least one memory write request, the first memory write request through a first buffer unit in the at least two buffer units; The data processing chip is further configured to read the first memory write request from the first cache unit, and process the first memory write request.
19. 19. A computing system comprising a processor including a receiving module, a distributing module, a cache module, and a data link module, the cache module including at least two cache units; The receiving module is used for receiving at least one memory writing request, wherein the memory writing request is a request sent by ports for writing data into a memory, and the number of the ports is at least two; The distribution module is configured to determine, for a first memory write request in the at least one memory write request, a first cache unit from the at least two cache units, and send the first memory write request to the first cache unit; the first caching unit is configured to cache the first memory write request, and send the first memory write request to the data link module; The data link module is configured to receive the first memory write request, and process the first memory write request.

Description

Processing module, request processing method applied to processing module, chip and system Technical Field The present application relates to the field of chips, and in particular, to a processing module, a request processing method applied to the processing module, a chip, and a system. Background In the current network architecture, buffers are typically used in TL (Transaction Layer ) of PCIe (PERIPHERAL COMPONENT INTERCONNECT EXPRESS, high speed serial computer expansion bus standard) to Buffer requests from multiple ports before sending to the data link layer for subsequent processing. In the related art, in the PCIe transaction layer, memory write requests from the ports share the same buffer. These memory write requests need to satisfy a first-in first-out mechanism. That is, after the last memory write request is completely sent to the data link layer, the next memory write request can be sent to the data link layer. However, in the above related art, the processing speed of the memory write request is slow. Disclosure of Invention The application provides a processing module, a request processing method, a chip and a system applied to the processing module. According to one aspect of the application, a processing module is provided, which comprises a receiving module, a distributing module, a cache module and a data link module, wherein the cache module comprises at least two cache units; The receiving module is used for receiving at least one memory writing request, wherein the memory writing request is a request sent by ports for writing data into a memory, and the number of the ports is at least two; The distribution module is configured to determine, for a first memory write request in the at least one memory write request, a first cache unit from the at least two cache units, and send the first memory write request to the first cache unit; the first caching unit is configured to cache the first memory write request, and send the first memory write request to the data link module; The data link module is configured to receive the first memory write request, and process the first memory write request. According to one aspect of the application, a request processing method applied to a processing module is provided, the processing module comprises a receiving module, a distributing module, a cache module and a data link module, the cache module comprises at least two cache units, and the method comprises the following steps: The receiving module receives at least one memory writing request, wherein the memory writing request is a request sent by ports for writing data into a memory, and the number of the ports is at least two; The distribution module determines a first cache unit from the at least two cache units for a first memory write request in the at least one memory write request, and sends the first memory write request to the first cache unit; The first caching unit caches the first memory writing request and sends the first memory writing request to the data link module; the data link module receives the first memory writing request and processes the first memory writing request. According to an aspect of the present application, there is provided a data processing chip; The data processing chip is used for receiving at least one memory writing request through the receiving module, wherein the memory writing request is a request sent by ports for writing data into a memory, and the number of the ports is at least two; the data processing chip is configured to determine, through a distribution module, a first cache unit from at least two cache units for a first memory write request in the at least one memory write request, and send the first memory write request to the first cache unit; the data processing chip is used for caching the first memory writing request through the first caching unit and sending the first memory writing request to the data link module; the data processing chip is used for receiving the first memory writing request through the data link module and processing the first memory writing request. According to one aspect of the present application, there is provided a computing system comprising a processor comprising a receiving module, a distributing module, a buffering module and a data link module, the buffering module comprising at least two buffering units; The receiving module is used for receiving at least one memory writing request, wherein the memory writing request is a request sent by ports for writing data into a memory, and the number of the ports is at least two; The distribution module is configured to determine, for a first memory write request in the at least one memory write request, a first cache unit from the at least two cache units, and send the first memory write request to the first cache unit; the first caching unit is configured to cache the first memory write request, and send the first memory write request to the data link module; The data