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CN-121979818-A - Control method based on self-adaptive storage backboard, self-adaptive storage backboard and device

CN121979818ACN 121979818 ACN121979818 ACN 121979818ACN-121979818-A

Abstract

The invention relates to a control method based on a self-adaptive storage backboard, the self-adaptive storage backboard and a device, wherein the method comprises the steps of collecting side band signals, out-of-band signals and PCIe link training and state of a state machine when a slot position insertion or topology change event is detected, and analyzing and processing the states to obtain a recognition result of a slot position; the method comprises the steps of configuring a high-speed differential cross matrix of a storage backboard based on a slot identification result to realize the purposes of switching slot attribution of a channel among a plurality of main control domains, splicing and binding or splitting the width of the channel according to requirements, sequentially adjusting and remapping the channel and polarity, switching a reference clock source of the slot to a matching mode through a phase alignment and gating technology, obtaining a link margin and an equalizer parameter of a PCIe link, writing the link margin and the equalizer parameter into a nonvolatile memory to form a slot image, and completing power supply and power supply of the slot under the control of a precharge and eFuse device. The invention can ensure the signal quality and reliability on the premise of supporting multi-protocol mixed insertion.

Inventors

  • SHENG LI

Assignees

  • 邦彦技术股份有限公司

Dates

Publication Date
20260505
Application Date
20260120

Claims (10)

  1. 1. The control method based on the self-adaptive storage backboard is characterized by comprising the following steps: Performing plug detection and protocol identification on the storage backboard, and collecting side band signals, out-of-band signals and PCIe link training and state of a state machine after detecting slot insertion or topology change events; Identifying and analyzing the side band signals, the out-of-band signals and the states of the PCIe link training and state machine to obtain the identification result of the slot position; Configuring a high-speed differential cross matrix of the storage backboard based on the identification result of the slot positions so as to realize the switching of the slot positions of channels among a plurality of main control domains, the splicing and binding or splitting treatment of the width of the channels according to the requirements, and the sequential adjustment and polarity remapping of the channels; based on the PCIe link training and the state of the state machine, switching the reference clock source of the slot position into a matching mode through a phase alignment and gating technology; Acquiring link margin and equalizer parameters of the PCIe link, and writing the link margin and equalizer parameters into a field replaceable unit or a nonvolatile memory to form a slot position image; And based on the slot position image, the power supply and the power supply of the slot position are completed under the control of the precharge and eFuse devices.
  2. 2. The method of claim 1, wherein the side band signals include an interface detect signal, a serial general purpose I/O signal, a sleep signal, a reset signal, and a clock request signal, the out-of-band signals include an initialization signal and a wake-up signal on a hard disk link, The identifying and analyzing the side band signal, the out-of-band signal, the PCIe link training and the state of the state machine, and the obtaining the identifying result of the slot comprises the following steps: The interface detection signal, the serial universal I/O signal, the dormant signal, the reset signal and the clock request signal are subjected to jitter removal processing through a side band signal acquisition unit respectively, and the state stability of each signal is judged; Detecting the envelope shapes and time intervals of an initialization signal and a wake-up signal on a hard disk link by using an out-of-band signal envelope detection unit to simulate a front-end circuit; Monitoring and analyzing the state transition process of the PCIe link training state machine within a preset time window by utilizing a time sequence sampling unit to obtain the PCIe link training and state analysis results of the state machine; And comprehensively analyzing the interface detection signal, the serial universal I/O signal, the dormancy signal, the reset signal, the clock request signal, the initialization signal and the wake-up signal on the hard disk link and the state analysis result of the PCIe link training and the state machine after the debouncing processing to obtain the target protocol type, the channel width and the rate grade of the slot position, and outputting the plugging event and the re-judging window control signal.
  3. 3. The method according to claim 2, wherein the configuring the high-speed differential cross matrix of the storage backplane based on the recognition result of the slot to implement switching slot assignment of channels between a plurality of master control domains, performing a splice or split process on the channel width as needed, and sequentially adjusting and remapping the channel and the polarity comprises: Configuring a high-speed differential cross matrix of the storage backboard based on the identification result of the slot, so that the high-speed differential cross matrix supports the channel to switch the slot attribution between a PCIe domain and an SAS domain, and the same slot is mapped to a CPU root port, a PCIe exchange chip or an SAS HBA/RAID controller to realize the dynamic multiplexing and multi-protocol mixed insertion of channel resources; According to the channel width in the slot position identification result, splicing and binding a plurality of x4 channels into x8 channels according to actual requirements, or splitting the x8 channels into a plurality of x4 channels; And forming an internal programmable switch network by using a mapping matrix of each pair of high-speed differential channels and the slot positions of the storage backboard, and controlling the on-off of the internal programmable switch network by using an MCU/CPLD through a register to realize remapping of the channel sequence and the polarity so as to adapt to wiring constraint of the main board and the storage backboard.
  4. 4. The method according to claim 2, wherein switching the reference clock source of the slot to the matching mode through the phase alignment and gating technique based on the identification result of the slot and the state of the PCIe link training and state machine comprises: acquiring PCIe link training and state of a state machine; when the state of the PCIe link training and state machine is a polling state or a recovery state, opening an always switching window; and smoothly switching the reference clock source used by the slot from the separated reference clock mode of the independent spread spectrum clock to the separated reference clock mode without the spread spectrum clock or switching the reference clock source from the separated reference clock mode without the spread spectrum clock back to the separated reference clock mode of the independent spread spectrum clock through the phase alignment and gating output circuit.
  5. 5. The method of claim 1, wherein the obtaining the link margin and equalizer parameters of the PCIe link, writing the link margin and equalizer parameters to a nonvolatile memory, and forming a slot image comprises: Taking a clock restorer or a signal repeater on the storage backboard as a core to perform online signal integrity test; And acquiring the link margin of the PCIe link, automatically adjusting continuous time linear equalizer, decision feedback equalizer and transmitting end pre-emphasis equalization parameters according to the test result of the signal integrity test, and writing the final stable parameters into a field replaceable unit or a nonvolatile memory to form a slot position image.
  6. 6. The method according to claim 5, wherein the automatically adjusting continuous-time linear equalizer, decision feedback equalizer, transmitting-side pre-emphasis equalization parameters according to the test result of the signal integrity test, and writing final stable parameters into a field replaceable unit or a nonvolatile memory to form a slot image comprises: Under the condition of maintenance window or service load permission, starting an equalizer self-adaptive flow, and injecting a pseudo-random binary sequence into a target channel or carrying out error rate and eye margin statistics by using operation data; Judging whether the link margin of the PCIe link meets a preset threshold according to the error rate and the eye pattern index obtained by the current test; When the link margin of the PCIe link does not meet the preset threshold, entering an equalizer parameter adjustment step, performing iterative optimization on the continuous time linear equalizer, the decision feedback equalizer and the transmitting end pre-emphasis equalization parameters, and repeating the online test and evaluation step; when the link margin of the PCIe link meets a preset threshold, writing the converged equalizer parameters into a field replaceable unit or a nonvolatile memory which is bound with the slot bit to form a signal integrity portrait of the slot bit.
  7. 7. The adaptive storage backplane-based control method of claim 1, wherein the powering up the slot based on the slot image under control of a precharge and eFuse device comprises: After detecting the insertion signal of the storage backboard, starting a pre-charging circuit to provide soft start for the load of the slot position; After the pre-charging is completed and the fact that the slot is free of short circuit is confirmed, an eFuse device is closed to perform main power supply, and power supply of the slot is powered on based on the slot image; if an overcurrent or short circuit is detected during power up, the eFuse device is opened and fault information is recorded.
  8. 8. An adaptive storage backplane for performing the adaptive storage backplane-based control method according to any one of claims 1 to 7, comprising: the protocol identification module is used for carrying out plug detection and protocol identification on the storage backboard, and collecting side band signals, out-of-band signals and states of a PCIe link training and state machine after a slot position insertion or topology change event is detected; the cross matrix module is used for configuring a high-speed differential cross matrix of the storage backboard based on the recognition result of the slot positions so as to realize the switching of the slot positions of channels among a plurality of main control domains, the splicing and binding or splitting treatment of the width of the channels as required, and the sequential adjustment and polarity remapping of the channels; The clock management module is used for switching the reference clock source of the slot position to a matching mode through a phase alignment and gating technology based on the PCIe link training and the state of the state machine; the self-adaptive module is used for acquiring the link margin and the equalizer parameter of the PCIe link, writing the link margin and the equalizer parameter into a field replaceable unit or a nonvolatile memory, and forming a slot position image; And the power supply and hot plug control module is used for completing power supply and power-on of the slot under the control of the precharge and eFuse device based on the slot image.
  9. 9. The adaptive storage backboard according to claim 8, further comprising a control and monitoring unit, wherein the main board BMC of the storage backboard is in bidirectional communication with the control and monitoring unit through an I2C bus, a PMBus and/or a GPIO interface, the control and monitoring unit is respectively connected with the protocol identification module, the cross matrix module, the clock management module, the adaptive module and the power supply and hot plug control module through a control bus, and the control and monitoring unit is used for issuing configuration instructions to each module and collecting running states, alarm information and self-checking results of each module, wherein the control and monitoring unit is an MCU or a CPLD.
  10. 10. A computer device comprising a memory and a processor, wherein the processor implements the method of any of claims 1 to 7 when executing a computer program stored in the memory.

Description

Control method based on self-adaptive storage backboard, self-adaptive storage backboard and device Technical Field The present invention relates to the field of computer storage hardware, and in particular, to a control method based on an adaptive storage backboard, and an apparatus thereof. Background With the explosive growth of cloud computing, big data and artificial intelligence services, the server and the storage system put forward the rigid demands of 'multi-protocol mixed-plug, high bandwidth, high reliability and zero interrupt maintenance' on the backboard. The conventional storage backboard is usually designed by hard-wired connection aiming at a single protocol (SAS or NVMe), the slot position and the main control port are fixedly mapped, the channel width is not variable, and the clock mode, the signal integrity parameter and the power supply time sequence are set at one time when leaving a factory. When the service needs to expand, upgrade or replace the hard disk with different protocols and different speed grades, the whole machine is powered down, the jumper/dial switch is manually adjusted, and even the whole backboard is replaced, so that the service is interrupted, the operation and maintenance cost is high, and the resource utilization rate is low. In order to alleviate the pain, the prior art attempts to introduce a "protocol auto-identification" function in the motherboard side or in the HBA/RAID card by detecting a PCIe link training state machine or out-of-band signal to determine the type of plugged device and then reallocating port resources via BIOS or HBA firmware. However, the scheme has the following defects that the multi-protocol compatibility mainly depends on a main control side, the backboard lacks autonomous capability, the high-speed channel topology is fixed, the resource utilization rate and expansibility are insufficient, the clock and signal integrity control is split, the high-speed rate capability is difficult to maintain in a multi-protocol environment, the power supply hot plug control and the protocol switching are disjoint, and the risk that burrs and surges affect the high-speed link exists. Disclosure of Invention The invention provides a control method based on an adaptive storage backboard, the adaptive storage backboard and a device, and aims to at least solve one of the technical problems in the prior art. The technical scheme of the invention is a control method based on a self-adaptive storage backboard, which comprises the following steps: Performing plug detection and protocol identification on the storage backboard, and collecting side band signals, out-of-band signals and PCIe link training and state of a state machine after detecting slot insertion or topology change events; Identifying and analyzing the side band signals, the out-of-band signals and the states of the PCIe link training and state machine to obtain the identification result of the slot position; Configuring a high-speed differential cross matrix of the storage backboard based on the identification result of the slot positions so as to realize the switching of the slot positions of channels among a plurality of main control domains, the splicing and binding or splitting treatment of the width of the channels according to the requirements, and the sequential adjustment and polarity remapping of the channels; based on the PCIe link training and the state of the state machine, switching the reference clock source of the slot position into a matching mode through a phase alignment and gating technology; Acquiring link margin and equalizer parameters of the PCIe link, and writing the link margin and equalizer parameters into a field replaceable unit or a nonvolatile memory to form a slot position image; And based on the slot position image, the power supply and the power supply of the slot position are completed under the control of the precharge and eFuse devices. According to some embodiments of the invention, the side-band signals include an interface detect signal, a serial general I/O signal, a sleep signal, a reset signal, and a clock request signal, the out-of-band signals include an initialize signal and a wake-up signal on a hard disk link, The identifying and analyzing the side band signal, the out-of-band signal, the PCIe link training and the state of the state machine, and the obtaining the identifying result of the slot comprises the following steps: The interface detection signal, the serial universal I/O signal, the dormant signal, the reset signal and the clock request signal are subjected to jitter removal processing through a side band signal acquisition unit respectively, and the state stability of each signal is judged; Detecting the envelope shapes and time intervals of an initialization signal and a wake-up signal on a hard disk link by using an out-of-band signal envelope detection unit to simulate a front-end circuit; Monitoring and analyzing the state transiti