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CN-121979819-A - SDIO slave device controller supporting multi-frame transmission and data transmission method

CN121979819ACN 121979819 ACN121979819 ACN 121979819ACN-121979819-A

Abstract

The invention discloses an SDIO slave device controller supporting multi-frame transmission and a data transmission method, wherein the controller is integrated with a DMA sending engine and a data buffer zone, and controls data flow through a linked list descriptor structure, so that the slave device can continuously send multi-frame data to a host, and generates interrupt notification to the host through driving a specific data line when the slave device is ready to send, and the corresponding method comprises the flow of configuring the descriptor, updating a length register, generating interrupt and continuously reading and writing data by the host in a plurality of modes. The invention realizes multi-frame continuous transmission from the SDIO slave device to the host, effectively eliminates interrupt waiting time between traditional single-frame transmission, and thereby remarkably improves bus utilization rate and data transmission efficiency.

Inventors

  • LIU GUANGXI
  • WU BIN
  • ZHOU XIAOPING

Assignees

  • 浙江科睿微电子技术有限公司

Dates

Publication Date
20260505
Application Date
20260123

Claims (9)

  1. 1. An SDIO slave device controller supporting multi-frame transmission, comprising: The system comprises a bus interface unit, a command processing unit, a data receiving and transmitting unit, a central register group unit, an interrupt state processing unit, a DMA (direct memory access) transmitting engine, a receiving and transmitting buffer zone and a clock domain crossing processing unit; The DMA sending engine is used for controlling the SDIO slave device to send single-frame or multi-frame data to the SDIO host through the linked list descriptor structure; The interrupt state processing unit is used for managing and reporting various internal state interrupts to the CPU; the receiving and transmitting buffer zone comprises TX_FIFO and RX_FIFO, wherein the available state information of the RX_FIFO is stored in the central register set unit for query by the SDIO host; the SDIO slave device controller generates an interrupt signal to the SDIO host through a DAT [1] signal line driving the SDIO bus when the data is ready to be transmitted.
  2. 2. The SDIO slave controller supporting multi-frame transfer of claim 1 further comprising a check unit for CRC checking commands and data transferred over the SDIO bus.
  3. 3. The SDIO slave controller supporting multi-frame transmission according to claim 1, wherein the central register bank unit includes CCCR registers, and wherein a frm_len register whose upper bits are used to indicate the unit of the value thereof is a data block or byte and whose lower bits are used to indicate the total length of data to be transmitted is provided in the CCCR register.
  4. 4. The SDIO slave device controller supporting multi-frame transmission of claim 1 wherein, The internal state interrupts managed by the interrupt state processing unit include at least one of a DMA write interrupt, a DMA read interrupt, a CMD53 read interrupt, and an rx_fifo non-empty interrupt, a data transfer interrupt, and a transfer error interrupt.
  5. 5. A data frame transmission method, characterized by being applied to the SDIO slave device controller according to any one of claims 1 to 4, the method comprising: configuring a linked list descriptor and starting the DMA sending engine; the DMA sending engine calculates the total length of data to be sent according to the linked list descriptor, and updates the total length of the data to the frm_len register; The SDIO slave device controller moves the data to be sent from the storage address indicated by the linked list descriptor to a TX_FIFO, and generates an interrupt signal to the SDIO host through a drive data line DAT [1 ]; The SDIO host responds to the interrupt signal and reads the frm_len register through a CMD52 command to acquire the total length of data, and reads single-frame or multi-frame data from the TX_FIFO in a single-block or multi-block data transmission mode.
  6. 6. The data frame transmission method according to claim 5, wherein after the generation of the interrupt signal to the SDIO host by driving the DAT [1] signal line, the SDIO host starts CMD53 command to read data from the tx_fifo in a single block or a multi block data transfer mode, the method further comprising: The SDIO host initiates a CMD52 command to read the frm_len register to obtain the total length of data.
  7. 7. The data frame transmission method of claim 5, wherein the linked list descriptor includes a transmission Buffer address, a transmission enable flag bit, and an address pointer to a next linked list descriptor.
  8. 8. A data frame receiving method, characterized by being applied to the SDIO slave device controller according to any one of claims 1 to 4, the method comprising: The SDIO host queries the availability state of RX_FIFO by accessing CCCR registers in the central register set unit; if the RX_FIFO has a residual space, the SDIO host transmits data to the RX_FIFO in a single-block or multi-block data transmission mode through a CMD53 command; after successfully receiving the first data block, the SDIO slave device controller replies a CRC ACK confirmation signal through an SDIO data line; The SDIO slave device controller sends an interrupt request to the CPU when the RX_FIFO data depth is non-zero, and the CPU starts data processing.
  9. 9. The data frame receiving method of claim 8, wherein the SDIO slave device controller transmits a BUSY signal to the SDIO host by driving an SDIO data line if a remaining space of the rx_fifo is lower than a preset threshold in transferring data to the rx_fifo.

Description

SDIO slave device controller supporting multi-frame transmission and data transmission method Technical Field The invention belongs to the technical field of SDIO interfaces, and particularly relates to an SDIO slave device controller supporting multi-frame transmission and a data transmission method. Background SD (Secure Digital) cards have the characteristics of small volume, high access speed, large storage capacity and the like, and are widely applied to electronic products such as mobile phones, walkman, electronic books, tablet computers and the like. Based on the SD card, an SDIO (Secure Digital Input and Output, secure digital input output) interface, an SDIO card and a corresponding SDIO bus protocol are provided, the SD interface is compatible, new command and interrupt interaction modes such as CMD52 and CMD53 are added, mobile and fixed equipment with the SD interface is supported, an SDHC (Secure DIGITAL HIGH CAPACITY) composite card is supported, the function of plug and play and the relatively complete upper SDIO protocol stack driving development capability are provided, and the method can be applied to Bluetooth, WIFI, GPS and the like. When the SDIO interface is used for data transmission, the following advantages are mainly achieved: (1) The SDIO interface adds CRC (Cyclic Redundancy Check ) protection in the transmitted data frame, and performs CRC check on the transmitted data, so that the accuracy of the data is ensured; (2) The SDIO interface supports three working modes, namely SPI (SERIAL PERIPHERAL INTERFACE ), SD1 and SD4, the biggest difference with the SD interface is that a low-speed standard is added, the SDIO interface works in the SPI mode and the SD1 mode, the data transmission speed is lower, the application of low-speed transmission can be met, when the SDIO interface works in the SD4 mode, the transmission speed is very high, the SDIO interface can be applied to occasions with higher transmission speed requirements, the three working modes are convenient to switch, and the switching of the working modes can be completed only by changing the configuration of corresponding registers through SDIO main equipment; (3) Each SDIO interface supports 7 input and output functional areas and 1 storage area at most, can complete expansion of seven functions, is integrated on the architecture of a system chip, and can conveniently and rapidly complete function expansion of the chip. Currently, an SDIO system includes an SDIO master device (SDIO host), an SDIO bus, and an SDIO slave device (SDIO slave), where the SDIO slave device implements data interaction between the SDIO slave device and the SDIO host through an SDIO slave device controller, and due to limitation of the existing SDIO slave device controller, the SDIO slave device can only send single frame data to the SDIO host at a time, and then interrupt for 30 to 40 microseconds, and send the single frame data again, so that transmission efficiency is low. Disclosure of Invention In order to solve the technical problems, the invention provides an SDIO slave device controller supporting multi-frame transmission and a data transmission method, so as to solve the problems in the prior art. To achieve the above object, the present invention provides an SDIO slave device controller supporting multi-frame transmission, including: The system comprises a bus interface unit, a command processing unit, a data receiving and transmitting unit, a central register group unit, an interrupt state processing unit, a DMA (Direct Memory Access ) transmitting engine, a receiving and transmitting buffer zone and a cross-clock domain processing unit; The DMA sending engine is used for controlling the SDIO slave device to send single-frame or multi-frame data to the SDIO host through the linked list descriptor structure; The interrupt state processing unit is used for managing and reporting various internal state interrupts to the CPU; The receiving and transmitting buffer zone comprises a TX_FIFO (transmitting first-in first-out buffer) and an RX_FIFO (receiving first-in first-out buffer), wherein the available state information of the RX_FIFO is stored in the central register unit for the SDIO host to inquire; the SDIO slave device controller generates an interrupt signal to the SDIO host through a DAT [1] signal line driving the SDIO bus when the data is ready to be transmitted. Optionally, the device further comprises a checking unit, wherein the checking unit is used for performing CRC check on the command and the data transmitted through the SDIO bus. Optionally, the central register set unit includes CCCR (Card Common Control Register ) registers, and a frm_len (frame length) register is set in the CCCR registers, where a high bit of the frm_len register is used to indicate that a unit of a value thereof is a data block or byte, and a low bit thereof is used to indicate a total length of data to be transmitted. Optionally, the internal state