CN-121979820-A - Bridge chip, intelligent computing network, command processing method and related products

Abstract

The disclosure provides a bridge chip, an intelligent computing network, a command processing method and related products, relates to the technical field of artificial intelligence, and particularly relates to the technical fields of cloud computing, large models, computing power and the like. The bridge chip comprises a first physical port, a second physical port, a control unit and a processing unit, wherein the first physical port is connected with a CPU and used for transmitting host protocol commands, the second physical port is connected with an AI chip and used for transmitting target equipment protocol commands, the control unit is connected with the first physical port and used for performing read-write operation on the host protocol commands in a command queue, and the processing unit is connected with the second physical port and the control unit and is provided with programmable software for executing conversion between the host protocol commands and the target equipment protocol commands by adopting the programmable software. The present disclosure may enable interconnection between a CPU supporting a host protocol and an AI chip supporting a device protocol.

Inventors

• LIU YUEJI
• CHI ZHIGANG
• LI YU
• LIU JINGLIANG
• LIU XINGXING

Assignees

• 北京百度网讯科技有限公司

Dates

Publication Date

20260505

Application Date

20251217

Claims (18)

1. 1. A bridge chip, comprising: the first physical port is connected with the CPU and used for transmitting host protocol commands; A second physical port connected to the AI chip for transmitting a target device protocol command, the target device protocol command being any one of a plurality of candidate device protocol commands supported by the second physical port; the control unit is connected with the first physical port and is used for performing read-write operation on the host protocol command in the command queue; And the processing unit is connected with the second physical port and the control unit, is provided with programmable software and is used for executing conversion between the host protocol command and the target equipment protocol command by adopting the programmable software.
2. 2. The chip of claim 1, further comprising: and the on-chip memory is connected with the interconnection bus and used for storing read-write data corresponding to the host protocol command and the target equipment protocol command.
3. 3. The chip of claim 2, wherein, The host protocol command comprises a host protocol command in a downlink direction sent by a CPU; the control unit comprises a first control unit; The command queue includes a first queue; The first control unit is configured to write a host protocol command in a downlink direction sent by the CPU into the first queue; The processing unit is specifically configured to read the host protocol command in the downstream direction from the first queue, and convert the host protocol command in the downstream direction into the target device protocol command by using the programmable software.
4. 4. The chip of claim 3, wherein, The host protocol command in the downlink direction is a read command in the downlink direction; The processing unit is further configured to: Receiving read data corresponding to the read command and sent by the AI chip through the second physical port, and writing the read data into the on-chip memory; The first control unit is further configured to: and reading the read data from the on-chip memory and sending the read data to the CPU through the first physical port.
5. 5. The chip of claim 1, wherein, The host protocol command comprises a host protocol command in the uplink direction; The control unit comprises a second control unit; the command queue includes a second queue; The processing unit is specifically configured to convert the target device protocol sent by the AI chip into an uplink host protocol command by using the programmable software, and write the uplink host protocol command into the second queue; the second control unit is configured to read the host protocol command in the uplink direction from the second queue, and send the host protocol command to the CPU.
6. 6. The chip of claim 5, wherein, The host protocol command in the uplink direction is a read command in the uplink direction; The second control unit is further configured to: Receiving read data corresponding to the read command and sent by the CPU through the first physical port, and writing the read data into the on-chip memory; The processing unit is further configured to: and reading the read data from the on-chip memory and sending the read data to the AI chip through the second physical port.
7. 7. The chip according to any one of claims 1 to 6, wherein, The first physical port is a CXL protocol port; The second physical port is an XLink protocol port.
8. 8. A mental arithmetic network, comprising: CPU, AI chip and bridge chip; The bridge chip is respectively connected with the CPU and the AI chip; wherein the bridge chip is as claimed in any one of claims 1 to 5.
9. 9. A command processing method, comprising: transmitting a host protocol command through a first physical port, wherein the first physical port is connected with a CPU; The method comprises the steps of transmitting a target equipment protocol command through a second physical port, wherein the second physical port is connected with an AI chip, and the target equipment protocol command is any one of a plurality of candidate equipment protocol commands supported by the second physical port; Performing read-write operation on the host protocol command in the command queue; And performing read-write operation on the host protocol command in the command queue, and performing conversion between the host protocol command and the target equipment protocol command by adopting programmable software.
10. 10. The method of claim 9, further comprising: and storing read-write data corresponding to the host protocol command and the target equipment protocol command through the on-chip memory.
11. 11. The method of claim 10, wherein, The host protocol command comprises a host protocol command in a downlink direction sent by a CPU; The command queue includes a first queue; the performing read-write operation on the host protocol command in the command queue includes: and writing the host protocol command in the downlink direction into the first queue.
12. 12. The method of claim 11, wherein, The host protocol command in the downlink direction is a read command in the downlink direction; The method further comprises the steps of: Receiving read data corresponding to the read command and sent by the AI chip through the second physical port, and writing the read data into the on-chip memory; and reading the read data from the on-chip memory and sending the read data to the CPU through the first physical port.
13. 13. The method of claim 10, wherein, The host protocol command comprises a host protocol command in the uplink direction; the command queue includes a second queue; The performing read-write operation on the host protocol command in the command queue, and performing conversion between the host protocol command and the target device protocol command by adopting programmable software, including: converting the target equipment protocol sent by the AI chip into an uplink host protocol command by adopting the programmable software, and writing the uplink host protocol command into the second queue; the performing read-write operation on the host protocol command in the command queue includes: And reading the host protocol command in the uplink direction from the second queue.
14. 14. The method of claim 13, wherein, The host protocol command in the uplink direction is a read command in the uplink direction; The method further comprises the steps of: Receiving read data corresponding to the read command and sent by the CPU through the first physical port, and writing the read data into the on-chip memory; and reading the read data from the on-chip memory and sending the read data to the AI chip through the second physical port.
15. 15. A command processing apparatus comprising: The first transmission module is used for transmitting the host protocol command through a first physical port, wherein the first physical port is connected with the CPU; The AI chip is connected with the second physical port, and the target equipment protocol command is any one of a plurality of candidate equipment protocol commands supported by the second physical port; The read-write module is used for performing read-write operation on the host protocol command in the command queue; And the processing module is used for performing read-write operation on the host protocol command in the command queue and executing conversion between the host protocol command and the target equipment protocol command by adopting programmable software.
16. 16. An electronic device, comprising: at least one processor, and A memory communicatively coupled to the at least one processor, wherein, The memory stores instructions executable by the at least one processor to enable the at least one processor to perform the method of any one of claims 9-14.
17. 17. A non-transitory computer readable storage medium storing computer instructions for causing the computer to perform the method of any one of claims 9-14.
18. 18. A computer program product comprising a computer program which, when executed by a processor, implements the method according to any of claims 9-14.

Description

Bridge chip, intelligent computing network, command processing method and related products Technical Field The disclosure relates to the technical field of artificial intelligence, in particular to the technical fields of cloud computing, large models, computing power and the like, and specifically relates to a bridge chip, an intelligent computing network, a command processing method, a device, equipment, a medium and a product. Background With the development of large language model (Large Language Model, LLM) technology, there is a need to achieve high-speed interconnection between a central processing unit (Central Processing Unit, CPU) and an artificial intelligence (ARTIFICIAL INTELLIGENCE, AI) chip. In the related art, a PCIe bus is generally adopted between the CPU and the AI chip, but the communication bandwidth is lower, and the LLM reasoning or training performance is affected. Disclosure of Invention The present disclosure provides a bridge chip, an intelligent computing network, a command processing method, an apparatus, a device, a medium and a product. According to one aspect of the disclosure, a bridge chip is provided, which comprises a first physical port connected with a CPU and used for transmitting host protocol commands, a second physical port connected with an AI chip and used for transmitting target equipment protocol commands, wherein the target equipment protocol commands are any one of a plurality of candidate equipment protocol commands supported by the second physical port, a control unit connected with the first physical port and used for performing read-write operation on the host protocol commands in a command queue, and a processing unit connected with the second physical port and the control unit and deployed with programmable software and used for executing conversion between the host protocol commands and the target equipment protocol commands by adopting the programmable software. According to another aspect of the disclosure, there is provided a smart computing network comprising a CPU, an AI chip and a bridge chip, the bridge chip connecting the CPU and the AI chip respectively, wherein the bridge chip is as described in any one of the above. According to another aspect of the disclosure, a command processing method is provided, which includes transmitting a host protocol command through a first physical port, the first physical port being connected to a CPU, transmitting a target device protocol command through a second physical port, the second physical port being connected to an AI chip, the target device protocol command being any one of a plurality of candidate device protocol commands supported by the second physical port, performing a read-write operation on the host protocol command in a command queue, and executing conversion between the host protocol command and the target device protocol command by using programmable software. According to another aspect of the disclosure, a command processing apparatus is provided, which includes a first transmission module configured to transmit a host protocol command through a first physical port, the first physical port being connected to a CPU, a second transmission module configured to transmit a target device protocol command through a second physical port, the second physical port being connected to an AI chip, the target device protocol command being any one of a plurality of candidate device protocol commands supported by the second physical port, a read-write module configured to perform a read-write operation on the host protocol command in a command queue, and a conversion module configured to perform conversion between the host protocol command and the target device protocol command using programmable software. According to another aspect of the present disclosure there is provided an electronic device comprising at least one processor and a memory communicatively coupled to the at least one processor, wherein the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the method of any one of the above aspects. According to another aspect of the present disclosure, there is provided a non-transitory computer readable storage medium storing computer instructions for causing the computer to perform the method according to any one of the above aspects. According to another aspect of the present disclosure, there is provided a computer program product comprising a computer program which, when executed by a processor, implements a method according to any of the above aspects. According to the embodiment of the disclosure, interconnection between the CPU supporting the host protocol and the AI chip supporting the device protocol can be realized. It should be understood that the description in this section is not intended to identify key or critical features of the embodiments of the disclosure, nor is it intended to be used to limit the scope of the disclo