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CN-121979822-A - MIPI DSI host controller with advanced DPI

CN121979822ACN 121979822 ACN121979822 ACN 121979822ACN-121979822-A

Abstract

The invention belongs to the technical field of display system interfaces, and particularly relates to an MIPI DSI host controller with an advanced DPI, which comprises an application layer, a protocol layer and a physical layer, wherein aDPI interfaces of the controller are compatible with a video mode and an adaptive command mode and support an AMBA APB bus to carry out internal register configuration and universal command transmission, the video mode and the adaptive command mode can cooperatively work or switch according to display requirements, the application layer receives pixel data from a processor from the aDPI interfaces and processes the pixel data, interface adaptation and clock domain isolation of a display data link before transmission are completed, the processed pixel data is sent to the protocol layer, the protocol layer realizes data transmission with the physical layer through cooperative work of internal modules of the protocol layer, and the invention realizes the unification of high-performance full-screen refreshing and ultra-low-power-consumption local updating on a single architecture and provides an excellent power consumption and performance balance scheme for an embedded display system with specific requirements.

Inventors

  • ZHANG CHENGCHANG
  • TIAN CHENGJIE
  • WANG MINGYAO

Assignees

  • 重庆邮电大学
  • 重庆拾加信息技术有限公司

Dates

Publication Date
20260505
Application Date
20260120

Claims (8)

  1. 1. The MIPI DSI host controller with the advanced DPI is characterized by comprising an application layer, a protocol layer and a physical layer, wherein aDPI interfaces of the controller are compatible with a video mode and an adaptive command mode, and support an AMBA APB bus to carry out internal register configuration and transmit a general command; The application layer receives pixel data from a processor and processes the pixel data to complete interface adaptation and clock domain isolation of a display data link before transmission and sends the processed pixel data to a protocol layer, wherein the application layer comprises aDPI interfaces, a aDPI video signal format interface module, two asynchronous FIFO control modules and an APB bus interface module, wherein the two asynchronous FIFO control modules are aDPI effective load FIFOs and aDPI cmd FIFO respectively; The protocol layer receives pixel data sent by the application layer, and realizes data transmission with the physical layer through the cooperative work of the internal modules of the protocol layer; The physical layer comprises a finite state machine of a physical layer interface controller, data channel allocation control logic, a channel management module, a high-speed transmission channel module and a low-speed transmission/reception channel module.
  2. 2. The MIPI DSI host controller with advanced DPI of claim 1, wherein in the application layer, the APB bus interface module acts as a configuration channel to receive and temporarily store pixel data parameters and display device configuration information from the processor via the APB bus; aDPI video signal format interface module as data and control signal channel to receive pixel data stream and control signal generated by image processing unit or other upstream module; The two asynchronous FIFO control modules are used for the cross-clock domain processing of pixel data and control signals respectively.
  3. 3. The MIPI DSI host controller with advanced DPI of claim 1, wherein in the protocol layer, the packet generation module receives pixel data of the application layer and encapsulates it into long or short packets that conform to DSI standards; The ECC generation unit generates an ECC check code for the packet header of the data packet; The CRC generation unit generates CRC check codes for the payloads of the long packets and respectively puts the CRC check codes into packet tails of the data packets; The error processing module continuously monitors the states of the asynchronous FIFO control module and the protocol layer, and when an error is detected, the error processing module intensively receives the abnormal information, pulls up the global error flag bit in a register overturning mode, and reports an error flag bit signal to an upper system to drive the upper system to execute retransmission operation; the ECC checking module is used for checking the packet head of the DSI data packet read back from the display equipment, has a 1-bit error correction function, and reports the error to the error processing module for further processing if single-bit or multi-bit errors occur in the ECC; The CRC module is used for checking the effective load of the DSI data packet read back from the display equipment, and reporting errors to the error processing module if errors exist; the data packet decoding module is used for analyzing and processing the DSI data packet read back from the display device.
  4. 4. A MIPI DSI host controller with advanced DPI according to claim 3, wherein the error handling module, while continuously monitoring status of the FIFO control module, if it detects that the FIFO control module is about to be full, the error handling module feeds back a full signal to the upper system to suspend data input to the upper system.
  5. 5. The MIPI DSI host controller with advanced DPI of claim 1, wherein ports of aDPI interfaces comprise: Timing and control signals pixel clock adpiclk, vertical sync adpivsync, horizontal sync adpihsync, data enable adpidataen, off adpishutdn, and color mode adpicolorm; Pixel data input adpipixdata; command mode signal tear effect feedback adpi _te and transmit enable adpi _dcs; other control signals-tearing effect enable adpi _ tearon and register configuration data to complete regbank configuration by APB.
  6. 6. The MIPI DSI host controller with advanced DPI of claim 1, wherein the pixel data transfer process of aDPI interface in video mode comprises: The upper layer system configuration controller works in a video mode, and configures internal register parameters through an AMBA APB bus; The display equipment is awakened through the APB bus interface module, and the physical layer is maintained in a state capable of entering high-speed transmission at any time; The upper layer system sends a pixel data stream and a corresponding control signal to the aDPI interface; the aDPI video signal format interface module performs standardization processing on the pixel data and the control signals, and the standardized pixel data and the standardized control signals are respectively cached in aDPI payload FIFO and aDPI command FIFO; the protocol layer packs the pixel data into DSI data packets according to the configured format and sends the DSI data packets to the physical layer; The physical layer transmits the DSI data packet to the physical layer receiver of the display equipment side in parallel through a plurality of configured differential data channels.
  7. 7. The MIPI DSI host controller with advanced DPI of claim 1, wherein the pixel data transfer process of aDPI interface in self-adaptive command mode comprises: The upper layer system configuration controller operates in a self-adaptive command mode; a control signal adpi _dcs rising edge is triggered to indicate that the signal is valid; a pixel counter inside the aDPI video signal format interface module starts to count valid pixels; When the counter reaches the set value of adpi _cmd_size, the Bao Manbiao flag is pulled up and transferred to the protocol layer, and the counter is cleared; the protocol layer generates a DSI command data packet after detecting the full flag bit; transmitting and sending the DSI command data packet to the display device through a DSI link; And when the transmission is finished, if the counter still has residual pixels, generating a last DSI command data packet by the residual pixels, and transmitting the last DSI command data packet to the display equipment through a DSI link.
  8. 8. The MIPI DSI host controller with advanced DPI of claim 7, wherein the process of operating the system configuration controller in the self-adapting command mode comprises: Configuring internal register parameters including a working mode, a payload size adpi _cmd_size of a DSI data packet and a pixel format through an AMBA APB bus; The upper layer system sends a pulse at adpi _ tearon port of aDPI interface; After the application layer detects the adpi _ tearon rising edge, the protocol layer generates a corresponding tearcmd data packet and sends the corresponding tearcmd data packet to the display device; the display device starts the tearing effect waiting for the upper layer system to send pixel data.

Description

MIPI DSI host controller with advanced DPI Technical Field The invention belongs to the technical field of display system interfaces, and particularly relates to an MIPI DSI host controller with an advanced DPI. Background The prior art MIPI DSI (display serial Interface) controller is compatible with MIPI DPI video mode and MIPI DBI (MIPI DISPLAY Bus Interface) command mode and supports configuration of its internal registers via AMBA APB Bus. It has a number of drawbacks, however, in particular the following: 1. the DSI architecture is limited by the mutual exclusivity of the DPI and DBI interfaces, resulting in two modes not working simultaneously. 2. In DPI video mode, the DSI controller needs to continually refresh the entire screen at a fixed frame rate. This mechanism has the inherent disadvantage that when the display content is only locally updated, the system still needs to be refreshed full screen, resulting in unnecessary power consumption and bandwidth waste. 3. In the DBI Command mode, the DSI controller may implement transmission of a small amount of pixel data through the MIPI DCS (MIPI DISPLAY Command Set) Command Set, but its transmission bandwidth is limited by the lower clock rate of the DBI interface (DPI clock can reach 250MHz, and DBI clock is typically 41 MHz). In view of the foregoing, a new MIPI DSI host controller is needed to solve the inherent defects of the conventional MIPI DSI controller in terms of mode mutual exclusion, local refresh power consumption and command mode bandwidth, and to achieve unification of high-performance full-screen refresh and ultra-low power consumption local refresh, so as to provide an excellent power consumption and performance balance scheme for embedded display systems with specific requirements. Disclosure of Invention Aiming at the defects existing in the prior art, the invention provides an MIPI DSI host controller with an advanced DPI, which comprises an application layer, a protocol layer and a physical layer, wherein aDPI interfaces of the controller are compatible with a video mode and an adaptive command mode, and support an AMBA APB bus to carry out internal register configuration and transmit a general command; The application layer receives pixel data from a processor from a aDPI interface and processes the pixel data, and the interface adaptation and clock domain isolation of a display data link before transmission are completed, and the processed pixel data is sent to a protocol layer; The protocol layer receives pixel data sent by the application layer, and realizes data transmission with the physical layer through the cooperative work of the internal modules of the protocol layer; The physical layer comprises a finite state machine of a physical layer interface controller, data channel allocation control logic, a channel management module, a high-speed transmission channel module and a low-speed transmission/reception channel module. Preferably, in the application layer, the APB bus interface module is used as a configuration channel, and receives and temporarily stores pixel data parameters and display device configuration information from the processor through the APB bus; aDPI video signal format interface module as data and control signal channel to receive pixel data stream and control signal generated by image processing unit or other upstream module; The two asynchronous FIFO control modules are used for the cross-clock domain processing of pixel data and control signals respectively. Preferably, in the protocol layer, the data packet generating module receives pixel data of the application layer and encapsulates the pixel data into a long packet or a short packet conforming to the DSI standard; The ECC generation unit generates an ECC check code for the packet header of the data packet; The CRC generation unit generates CRC check codes for the payloads of the long packets and respectively puts the CRC check codes into packet tails of the data packets; The error processing module continuously monitors the states of the asynchronous FIFO control module and the protocol layer, and when an error is detected, the error processing module intensively receives the abnormal information, pulls up the global error flag bit in a register overturning mode, and reports an error flag bit signal to an upper system to drive the upper system to execute retransmission operation; the ECC checking module is used for checking the packet head of the DSI data packet read back from the display equipment, has a 1-bit error correction function, and reports the error to the error processing module for further processing if single-bit or multi-bit errors occur in the ECC; The CRC module is used for checking the effective load of the DSI data packet read back from the display equipment, and reporting errors to the error processing module if errors exist; the data packet decoding module is used for analyzing and processing the DSI data packet read back f