CN-121979826-A - Communication circuit and communication system

CN121979826ACN 121979826 ACN121979826 ACN 121979826ACN-121979826-A

Abstract

The application discloses a communication circuit and a communication system, the communication circuit comprises a controller, a serial transceiver chip, a signal conversion circuit, a unidirectional conductive circuit, a delay circuit and a bias circuit. The signal conversion circuit outputs an inverted signal of the serial transmission pin. The delay circuit delays the signal of the serial transmitting pin and the inverted signal. The rising time of the signal of the receiving enable pin is earlier than the rising time of the signal of the transmitting enable pin, the rising time of the signal of the transmitting enable pin is earlier than the falling time of the signal of the transmitting data input pin, the falling time of the signal of the transmitting enable pin is later than the rising time of the signal of the transmitting data input pin, and the falling time of the signal of the receiving enable pin is later than the falling time of the signal of the transmitting enable pin. The bias circuit pulls up the first differential signal pin and pulls down the second differential signal pin. By the mode, serial communication can be realized based on two pins of the controller, so that I/O resources are saved.

Inventors

QIN GENG
MA HUI
PEI BINBIN
MENG ZHONGPING

Assignees

深圳市德兰明海新能源股份有限公司

Dates

Publication Date: 20260505
Application Date: 20260109

Claims (10)

1. A communication circuit, comprising: the controller comprises a serial receiving pin and a serial transmitting pin; The serial transceiver chip comprises a transmission data input pin, a reception data output pin, a transmission enabling pin, a reception enabling pin, a first differential signal pin and a second differential signal pin, wherein a frame structure when the controller and the serial transceiver chip perform serial communication comprises a start bit, and the start bit is of a low level; The signal conversion circuit is electrically connected with the serial transmission pin and is used for outputting an inverted signal of the signal output by the serial transmission pin; A unidirectional conductive circuit, a first end of the unidirectional conductive circuit being electrically connected to the signal conversion circuit, the unidirectional conductive circuit being configured to inhibit current flow from a second end of the unidirectional conductive circuit to the first end of the unidirectional conductive circuit; The delay circuit is electrically connected with the second end of the unidirectional conductive circuit, the receiving enabling pin, the transmitting enabling pin, the serial transmitting pin and the transmitting data input pin respectively, and is used for delaying signals output by the serial transmitting pin and outputting the signals to the transmitting data input pin, and is used for delaying the inverted signals and outputting the signals to the receiving enabling pin and the transmitting enabling pin; Wherein in one period, a rising time of the signal input to the reception enable pin is earlier than a rising time of the signal input to the transmission enable pin, the rising time of the signal input to the transmission enable pin is earlier than a falling time of the signal input to the transmission data input pin, the falling time of the signal input to the transmission enable pin is later than the rising time of the signal input to the transmission data input pin, the falling time of the signal input to the reception enable pin is later than the falling time of the signal input to the transmission enable pin, the rising time is a time when the voltage of the signal increases to pass through a high level threshold voltage, and the falling time is a time when the voltage of the signal decreases to pass through a low level threshold voltage; And the bias circuit is electrically connected with the first differential signal pin and the second differential signal pin respectively and is used for pulling up the first differential signal pin and pulling down the second differential signal pin.
2. The communication circuit of claim 1, wherein the signal conversion circuit comprises an not gate; the input end of the NOT gate is electrically connected with the serial transmitting pin, and the output end of the NOT gate is electrically connected with the unidirectional conductive circuit.
3. The communication circuit of claim 1, wherein the signal conversion circuit comprises a first switching tube and a first resistor; The first end of the first switching tube is electrically connected to the serial transmitting pin through the first resistor, the second end of the first switching tube is electrically connected with a first power supply, and the third end of the first switching tube is electrically connected with the delay circuit, wherein the first switching tube is a PNP triode; Or alternatively The first end of the first switch tube and the first end of the first resistor are electrically connected with the serial transmission pin, the second end of the first switch tube and the second end of the first resistor are electrically connected with the first power supply, and the third end of the first switch tube is electrically connected with the delay circuit, wherein the first switch tube is a PMOS tube.
4. The communication circuit of claim 1, wherein the unidirectional conductive circuit comprises a diode; The anode of the diode is electrically connected with the signal conversion circuit, and the cathode of the diode is electrically connected with the delay circuit.
5. The communication circuit of claim 1, wherein the delay circuit comprises a second resistor and a first capacitor; The first end of the second resistor is electrically connected with the serial transmitting pin, the second end of the second resistor and the first end of the first capacitor are both electrically connected with the transmitting data input pin, and the second end of the first capacitor is grounded.
6. The communication circuit of claim 1, wherein the delay circuit comprises a third resistor and a second capacitor; The first end of the third resistor is electrically connected with the second end of the unidirectional conductive circuit, the second end of the third resistor and the first end of the second capacitor are both electrically connected with the sending enabling pin, and the second end of the second capacitor is grounded.
7. The communication circuit of claim 1, wherein the delay circuit comprises a fourth resistor and a third capacitor; The first end of the fourth resistor is electrically connected with the second end of the unidirectional conductive circuit and the receiving enabling pin, the second end of the fourth resistor is grounded, and the third capacitor is connected with the fourth resistor in parallel.
8. The communication circuit of claim 1, wherein the bias circuit further comprises a fifth resistor and a sixth resistor; The fifth resistor is electrically connected between a first power supply and the first differential signal end, and the sixth resistor is electrically connected between the second differential signal end and ground.
9. The communication circuit according to any one of claims 1-8, wherein the communication circuit further comprises a seventh resistor; the first end of the seventh resistor is electrically connected with a first power supply, and the second end of the seventh resistor is electrically connected with the serial receiving pin and the transmitting data input pin.
10. A communication system comprising a first bus, a second bus, an eighth resistor, a ninth resistor, a fourth capacitor, a fifth capacitor, and a plurality of communication circuits according to any one of claims 1-9; The first differential signal end of the serial transceiver chip in each communication circuit is electrically connected to the first bus, and the second differential signal end of the serial transceiver chip in each communication circuit is electrically connected to the second bus; The first end of the first bus is electrically connected to the first end of the second bus through an eighth resistor and a fourth capacitor which are connected in series, and the second end of the first bus is electrically connected to the second end of the second bus through a ninth resistor and a fifth capacitor which are connected in series.

Description

Communication circuit and communication system Technical Field The embodiment of the application relates to the technical field of communication, in particular to a communication circuit and a communication system. Background RS-485 is used as a differential serial communication standard widely applied to industrial control, intelligent instruments and terminal equipment of the Internet of things, and has the advantages of strong anti-interference capability, long transmission distance, support of multipoint networking and the like. Typical RS-485 communication systems usually employ half duplex mode, and conversion between TTL/CMOS level and differential signal is achieved by serial transceiver chips (e.g., MAX485, SP3485, etc.). Such serial transceiver chips generally include a transmit enable terminal and a receive enable terminal for controlling a data transmission direction, in which the transceiver is in a transmit state when the transmit enable terminal is at a high level and in a receive state when the receive enable terminal is at a low level. In the conventional design, the microcontroller (Microcontroller Unit, MCU) needs to occupy one or two additional GPIO pins to dynamically switch the transmit/receive direction, so as to avoid bus collision. However, in many cost-sensitive application scenarios, such as embedded sensor nodes, small smart meters, environment monitoring terminals, etc., a low-cost single-chip microcomputer with a small number of pins is often selected. The I/O resources of such MCUs are extremely tight, often all available pins have been used for analog sampling, digital input/output, power management or communication interface functions. In such systems, the pin resource pressure is significantly exacerbated if a GPIO pin is still required to be allocated separately for controlling the directional switching of the serial transceiver chip. Disclosure of Invention The embodiment of the application provides a communication circuit and a communication system, which can realize serial communication based on two pins of a controller so as to save I/O resources. In a first aspect, an embodiment of the present application provides a communication circuit, including a controller, a serial transceiver chip, a signal conversion circuit, a unidirectional conductive circuit, a delay circuit, and a bias circuit. The controller includes a serial receive pin and a serial transmit pin. The serial transceiver chip comprises a transmission data input pin, a reception data output pin, a transmission enabling pin, a reception enabling pin, a first differential signal pin and a second differential signal pin, wherein a frame structure during serial communication between the controller and the serial transceiver chip comprises a start bit, and the start bit is of a low level. The signal conversion circuit is electrically connected with the serial transmission pin and is used for outputting an inverted signal of the signal output by the serial transmission pin. The first end of the unidirectional conductive circuit is electrically connected to the signal conversion circuit, and the unidirectional conductive circuit is used for inhibiting current from flowing from the second end of the unidirectional conductive circuit to the first end of the unidirectional conductive circuit. The delay circuit is electrically connected with the second end of the unidirectional conductive circuit, the receiving enabling pin, the transmitting enabling pin, the serial transmitting pin and the transmitting data input pin respectively, and is used for delaying signals output by the serial transmitting pin and outputting the signals to the transmitting data input pin, and is used for delaying inverted signals and outputting the signals to the receiving enabling pin and the transmitting enabling pin. Wherein, in one period, the rising time of the signal input to the receiving enable pin is earlier than the rising time of the signal input to the transmitting enable pin, the rising time of the signal input to the transmitting enable pin is earlier than the falling time of the signal input to the transmitting data input pin, the falling time of the signal input to the transmitting enable pin is later than the rising time of the signal input to the transmitting data input pin, the falling time of the signal input to the receiving enable pin is later than the falling time of the signal input to the transmitting enable pin, the rising time is the time when the voltage of the signal increases to pass through the high level threshold voltage, and the falling time is the time when the voltage of the signal decreases to pass through the low level threshold voltage. The bias circuit is electrically connected with the first differential signal pin and the second differential signal pin respectively, and is used for pulling up the first differential signal pin and pulling down the second differential signal pin. In one or more embodimen