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CN-121979830-A - Data interaction method, device, equipment and medium of multi-core heterogeneous chip

CN121979830ACN 121979830 ACN121979830 ACN 121979830ACN-121979830-A

Abstract

The invention provides a data interaction method, a device, equipment and a medium of a multi-core heterogeneous chip, wherein the method comprises the steps of sending a control command to a small core through a large core so as to enable the small core to perform initialization configuration; and processing the peripheral data and/or the inter-core data by the small core to obtain target data, and transmitting the target data to the large core or the small core. The multi-core heterogeneous chip can adapt to different application scenes by acquiring peripheral data and/or inter-core data through the corelets, has good universality, is used for processing data in series or in parallel through the corelets, has various inter-core data interaction, is compatible with each scene of data interaction, has high flexibility and good expansibility, and can directly perform data interaction between the corelets and the corelets, and has high communication efficiency.

Inventors

  • XU DONG
  • CAI YONGHENG

Assignees

  • 珠海全志科技股份有限公司

Dates

Publication Date
20260505
Application Date
20251231

Claims (12)

  1. 1. The data interaction method of the multi-core heterogeneous chip is characterized by being applied to a multi-core heterogeneous chip system, wherein the multi-core heterogeneous chip system comprises a large core and a plurality of small cores, the large core and the small cores are connected through buses, and the data interaction method of the multi-core heterogeneous chip comprises the following steps: sending a control command to the small core through the large core so as to enable the small core to perform initialization configuration; Acquiring peripheral data and/or inter-core data through the initialized small core, wherein the inter-core data represents data generated through the large core or the small core; And processing the peripheral data and/or the inter-core data through the small core to obtain target data, and transmitting the target data to the large core or the small core, wherein the data generated by the small core is processed in series by a plurality of small cores to obtain the target data, and the data generated by the large core is processed in series or in parallel by a plurality of small cores to obtain the target data.
  2. 2. The method for data interaction of a heterogeneous multi-core chip according to claim 1, wherein the sending, by the large core, a control command to the small core to cause the small core to perform initialization configuration includes: creating initialization threads when the small cores are started, wherein the number of the initialization threads is configured according to the number of the large-core multi-process; respectively establishing a control channel with a plurality of small cores by calling a cross-core control interface through the large core; The initialization configuration is called through the big core, the big core sends an initialization control command to the small core through the control channel, and meanwhile, a cross-core data transmission interface is called to establish a data transmission channel; the control channel is called through the multiprocess of the big core to send the initialization control command to a plurality of small cores so that the small cores perform initialization configuration; creating a command processing thread between the small core and the large core through the initialization thread; The control command is sent to the corelet through the command processing thread so that the corelet can be configured in an initializing mode; and starting data transmission through the big core, and creating a data processing thread and a data transmission thread after the small core receives a starting transmission command through the command processing thread.
  3. 3. The method for data interaction of a multi-core heterogeneous chip according to claim 2, wherein creating a command processing thread between the small core and the large core by the initialization thread comprises: Calling a first cross-core control interface of the small core end through the initialization thread, and waiting for the large core to call a second cross-core control interface to create a control channel; invoking a second cross-core control interface which is the same as the first cross-core control interface through the big core, wherein the second cross-core control interface is positioned at the big core end; after the first cross-core control interface and the second cross-core control interface are successfully invoked, the initialization thread can create the command processing thread and automatically clear the initialization thread.
  4. 4. The method for data interaction of a multi-core heterogeneous chip according to claim 2, wherein establishing the data transmission channel between the large core and the small core comprises: Calling initialization configuration through the big core, calling a first cross-core data interface of the small core end after the small core end receives an initialization command through the command processing thread, and waiting for the big core to call a second cross-core data interface to create a data transmission channel; Invoking a second cross-core data interface which is the same as the first cross-core data interface through the big core, wherein the second cross-core data interface is positioned at the big core end; After the first cross-core data interface and the second cross-core data interface are successfully called, the large core starts cross-core data transmission; The data transmission channel is divided into data transmission from big core to small core or data transmission types from small core to big core according to the requirements; The number of the data transmission channels is configured by the number of the large-core multi-process, and the data transmission channels can independently and parallelly transmit different types of data.
  5. 5. The method for data interaction of a heterogeneous multi-core chip according to claim 2, wherein after the corelet receives an open transmission command through the command processing thread, creating the data processing thread and the data transmission thread comprises: processing the peripheral data and/or the inter-core data in real time through the data processing thread; Transmitting the data processed by the data processing thread to the small core or the large core through the data transmission thread; After the small core receives the start transmission command through the command processing thread, after the data transmission thread and the data transmission thread are built, a feedback command is sent to the large core through a cross-core command interface to indicate that the small core is ready for preparation, and the data transmission function of the large core is started.
  6. 6. The method for data interaction of a multi-core heterogeneous chip according to claim 2, wherein after the initialization configuration of the corelet, the method further comprises: Establishing a cross-core transmission component among a plurality of the corelets; and transmitting data among the plurality of corelets in turn through the cross-core transmission component so that the plurality of corelets process the data in series.
  7. 7. The method for data interaction of multi-core heterogeneous chips according to claim 1, wherein the obtaining peripheral data and/or inter-core data by the initialized corelet comprises: Acquiring the peripheral data through a first sub-core; acquiring first data of the first sub-core through a second sub-core, wherein the first data belongs to the inter-core data, and the first data is obtained after the peripheral data is processed through the first sub-core; Processing the first data of the first sub-core through a second sub-core to obtain second data, wherein the second data belongs to the inter-core data; and acquiring third data of the large core through a third sub-core, wherein the third data belongs to the inter-core data, and the first sub-core, the second sub-core and the third sub-core represent the small cores of different types.
  8. 8. The method for data interaction of a multi-core heterogeneous chip according to claim 1, wherein in a case where the multi-core heterogeneous chip is dormant, the method further comprises: Sending a low power consumption command to a fourth sub-core through the large core so as to enable the fourth sub-core to enter a low power consumption mode, wherein the fourth sub-core characterizes the small core used for acquiring the peripheral data during the dormancy of the multi-core heterogeneous chip; sending a sleep command or a close command to a fifth sub-core through the large core so that the fifth sub-core goes to sleep or close, wherein the fifth sub-core characterizes the small core going to sleep or close; after the fifth sub-core enters sleep or shuts down, the large core enters a low power mode or sleep.
  9. 9. The method for data interaction of a multi-core heterogeneous chip according to claim 8, wherein in a case where the multi-core heterogeneous chip wakes up, the method further comprises: When the peripheral data received by the fourth sub-core is wake-up data, waking up the large core to exit from sleep or exit from a low power consumption mode through the fourth sub-core, and waking up the fourth sub-core to exit from the low power consumption mode through the large core; under the condition that the awakening data represents primary awakening, the large core awakens a hardware resource, data generated by the fourth sub-core is stored into the hardware resource, the fourth sub-core is controlled to continuously receive and process the awakening data, and whether secondary awakening is entered is judged by the fourth sub-core processing the awakening data; and after judging success, under the condition of entering a secondary wake-up, sending a command for entering a normal mode to the fourth sub-core through the big core, waking up or starting the fifth sub-core to enter the normal mode, and then entering the normal mode by the big core.
  10. 10. A data interaction device of a multi-core heterogeneous chip, characterized in that the data interaction device applied to the multi-core heterogeneous chip according to any one of claims 1 to 9 comprises: the first module is used for sending a control command to the small core through the large core so as to enable the small core to perform initialization configuration; the second module is used for acquiring peripheral data and/or inter-core data through the initialized small core, and the inter-core data represents data generated through the large core or the small core; and the third module is used for processing the peripheral data and/or the inter-core data through the small cores to obtain target data and transmitting the target data to the large cores or the small cores, wherein the target data is obtained after the data generated by the small cores are processed in series by a plurality of small cores, and the target data is obtained after the data generated by the large cores are processed in series or in parallel by a plurality of small cores.
  11. 11. An electronic device, comprising: At least one processor; At least one memory for storing at least one program; the at least one program, when executed by the at least one processor, causes the at least one processor to implement the data interaction method of the multi-core heterogeneous chip of any of claims 1 to 9.
  12. 12. A computer readable storage medium having stored therein program instructions which when executed by a processor implement the data interaction method of a multi-core heterogeneous chip according to any of claims 1 to 9.

Description

Data interaction method, device, equipment and medium of multi-core heterogeneous chip Technical Field The present invention relates to, but not limited to, the field of communications technologies, and in particular, to a method, an apparatus, a device, and a medium for data interaction of a multi-core heterogeneous chip. Background With the rapid development of integrated circuit technology, chip design schemes tend to be heterogeneous with multiple cores, often consisting of multiple large cores and multiple small cores. Different cores in the heterogeneous multi-core platform define different responsibilities and run respective independent OS (Operating systems). At present, inter-core communication of multi-core heterogeneous chips in the market is completed through specific hardware or shared memory and interrupt, the communication quantity is limited due to the limitation of the hardware, the expansibility is poor, the shared memory and the interrupt need two memories to communicate, only large cores are supported to copy data to the shared memory, small cores are copied to the shared memory after reading data, and the communication efficiency is low. Disclosure of Invention The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims. The embodiment of the invention mainly aims to provide a data interaction method, device, equipment and medium of a multi-core heterogeneous chip, which can improve the communication efficiency and expansibility of the multi-core heterogeneous chip. In a first aspect, an embodiment of the present invention provides a data interaction method of a multi-core heterogeneous chip, which is applied to a multi-core heterogeneous chip system, where the multi-core heterogeneous chip system includes a large core and a plurality of small cores, the large core and the small cores are connected through a bus, and the data interaction method of the multi-core heterogeneous chip includes: sending a control command to the small core through the large core so as to enable the small core to perform initialization configuration; Acquiring peripheral data and/or inter-core data through the initialized small core, wherein the inter-core data represents data generated through the large core or the small core; And processing the peripheral data and/or the inter-core data through the small core to obtain target data, and transmitting the target data to the large core or the small core, wherein the data generated by the small core is processed in series by a plurality of small cores to obtain the target data, and the data generated by the large core is processed in series or in parallel by a plurality of small cores to obtain the target data. The data interaction method of the multi-core heterogeneous chip at least has the advantages that peripheral data and/or inter-core data are obtained through the small cores, so that the multi-core heterogeneous chip can adapt to different application scenes, the universality is good, the data are processed through the plurality of small cores in series or in parallel, the inter-core data interaction is various, the data interaction scenes are compatible, the flexibility is high, the expansibility is good, the data interaction is directly carried out between the large cores and the small cores, and the communication efficiency is high. In some optional embodiments, the sending, by the big core, a control command to the small core to cause the small core to perform an initialization configuration includes: creating the initialization threads when the small cores are started, wherein the number of the initialization threads is configured according to the number of the large-core multi-process; respectively establishing a control channel with a plurality of small cores by calling a cross-core control interface through the large core; Calling initialization configuration through the big core, sending an initialization control command to the small core through the control channel by the big core, and calling a cross-core data transmission interface to establish the data transmission channel; the control channel is called through the multiprocess of the big core to send the initialization control command to a plurality of small cores so that the small cores perform initialization configuration; creating a command processing thread between the small core and the large core through the initialization thread; The control command is sent to the corelet through the command processing thread so that the corelet can be configured in an initializing mode; starting data transmission through the big core, and creating a data processing thread and a data transmission thread after the small core receives a starting transmission command through the command processing thread; in some alternative embodiments, the creating, by the initialization thread, a command processing thread between the small c