CN-121979833-A - Star-earth on-orbit configuration method and system for anti-fuse FPGA

CN121979833ACN 121979833 ACN121979833 ACN 121979833ACN-121979833-A

Abstract

The invention provides a satellite-ground on-orbit configuration method and a system for an anti-fuse FPGA, which relate to the technical field of aerospace electronics, wherein the method comprises the steps of obtaining FPGA configuration file data; the method comprises the steps of performing satellite-to-ground uploading coding processing to obtain ground preparation data, uploading the ground preparation data to a spacecraft through a space link, performing data processing to the ground preparation data to obtain configurable data, writing the configurable data into a standby configuration area of a target FPGA, performing integrity verification to the data of the standby configuration area, triggering the target FPGA to be changed from the main configuration area to the standby configuration area, performing functional verification test to the changed target FPGA, returning a verification result and state information to the ground when the test is passed, completing satellite-to-ground uploading and satellite-to-satellite file data transmission tasks, and sending a rollback instruction to the target FPGA when the test is not passed, controlling the target FPGA to be changed back from the standby configuration area to the main configuration area and returning the rollback result and fault information to the ground.

Inventors

ZHOU YANG
JIN GEHUI
HUANG CHENLIN
BAO JIAHUI

Assignees

浙江众星志连科技有限责任公司
众星志连(贵阳)航天科技有限责任公司

Dates

Publication Date: 20260505
Application Date: 20251224

Claims (10)

1. A star-to-ground in-orbit configuration method for an antifuse FPGA, comprising: S1, acquiring FPGA configuration file data; s2, performing planet ground uploading coding processing on the FPGA configuration file data to obtain ground preparation data; s3, uploading the ground preparation data to a spacecraft through a space link; S4, in the spacecraft, carrying out data processing on the ground preparation data to obtain configurable data; s5, writing the configurable data into a standby configuration area of a target FPGA; s6, carrying out integrity check on all data in the standby configuration area; s7, triggering a soft switching instruction after the integrity check, and controlling the target FPGA to switch from a main configuration area to the standby configuration area; S8, performing function verification test on the switched target FPGA to obtain a function verification test result which comprises that the function verification test passes and that the function verification test fails; S9, returning the verification result and the state information to the ground when the function verification test passes, and finishing the satellite-ground uploading and the satellite-internal file data transmission task; And S10, when the function verification test fails, a rollback instruction is sent to the target FPGA, the target FPGA is controlled to switch back to the main configuration area from the standby configuration area, and a rollback result and fault information are returned to the ground.
2. The star-to-ground on-orbit configuration method for an antifuse FPGA of claim 1, wherein S2 specifically comprises: S201, performing LDPC coding and Turbo coding on the FPGA configuration file data to obtain coded data; s202, dividing the coded data according to a preset size to form a plurality of data block frames; s203, storing the data block frames to a ground transmitting end buffer area according to the numbering sequence of a plurality of the data block frames; S204, generating a data transmission task based on the total block number of the data block frame, the corresponding FPGA number and the coding rule; s205, initializing ground control task parameters according to the data transmission task, and loading a preset fault code library; S206, initializing a monitoring interface based on the ground control task parameters and the preset fault code library, and establishing a real-time communication link; S207, sending a pre-starting instruction to a transmitting end through the real-time communication link; And S208, according to the pre-starting instruction, the transmitting end feeds back a ready signal to judge that the ground preparation data is ready.
3. The star-to-ground on-orbit configuration method for an antifuse FPGA of claim 1, wherein S3 specifically comprises: s301, performing planetary bi-directional interaction through a note number starting instruction, and establishing the space link; s302, transmitting the data block frame in the ground preparation data to the spacecraft through the space link, and controlling the transmission process based on state feedback returned by the spacecraft.
4. The star-to-ground on-orbit configuration method for an antifuse FPGA of claim 3, wherein S301 specifically comprises: s3011, generating the betting start instruction based on the ground control task parameters; S3012, demodulating and filtering the number of bets starting instruction through the spacecraft to obtain a recovery instruction; S3013, performing CRC check on the recovery instruction; S3014, when CRC passes, extracting a target FPGA number in the recovery instruction, and inquiring the state of a corresponding FPGA in the spacecraft; S3015, when the target FPGA is in an idle state, generating a ready response and transmitting the ready response back to the ground; S3016, after receiving the readiness response in a preset time, the ground updates the monitoring state to complete the establishment of the space link, and when the readiness response is not received in a timeout, the betting start instruction is retransmitted.
5. The star-to-ground on-orbit configuration method for an antifuse FPGA of claim 1, wherein S4 specifically comprises: s401, writing a data block frame in the ground preparation data into a plurality of storage units; S402, judging whether the data in each storage unit accords with preset comparison logic, if so, judging that the consistent data obtained by comparison is the configurable data, and if not, executing error correction processing to recover the configurable data.
6. The star-to-ground on-orbit configuration method for an antifuse FPGA of claim 1, wherein S5 specifically comprises: s501, receiving a ground start configuration writing instruction; s502, responding to the starting configuration writing instruction, and writing the configurable data into the standby configuration area block by block according to the numbering sequence of the data block frames; and S503, recording an interruption position when interruption occurs in the writing process, and continuing writing from the interruption position after recovery.
7. The star-to-ground on-orbit configuration method for an antifuse FPGA of claim 1, wherein S6 specifically comprises: s601, calculating check values of all data in the standby configuration area; S602, comparing the check value with a corresponding check value of the FPGA configuration file data; s603, extracting logic feature codes of data in the standby configuration area; s604, comparing the logic feature code with the corresponding logic feature code of the FPGA configuration file data; s605, judging whether the comparison of the check value and the logic feature code is passed or not, if so, judging that the integrity check is passed, and if not, judging that the integrity check is not passed.
8. The star-to-ground on-orbit configuration method for an antifuse FPGA of claim 1, wherein S8 specifically comprises: s801, establishing a communication link with the switched FPGA through an on-board state monitoring unit; s802, carrying out logic output test and interface response test on the switched FPGA through the communication link; S803, judging whether the logic output test and the interface response test meet expectations, if so, judging that the function verification test passes, and if not, judging that the function verification test fails.
9. A star-to-ground on-orbit configuration system for an anti-fuse FPGA is characterized by comprising a processor and a memory; The memory stores a program or instructions executable on the processor, which when executed by the processor, implement the steps of the star-to-ground on-orbit configuration method for an antifuse FPGA as claimed in any one of claims 1to 8.
10. A readable storage medium, characterized in that it has stored thereon a program or instructions which, when executed by a processor, implement the steps of the satellite-to-ground on-orbit configuration method for an antifuse FPGA according to any one of claims 1 to 8.

Description

Star-earth on-orbit configuration method and system for anti-fuse FPGA Technical Field The invention relates to the technical field of aerospace electronics, in particular to a satellite-ground on-orbit configuration method and system for an anti-fuse FPGA. Background Modern spacecraft increasingly rely on Field Programmable Gate Arrays (FPGAs) to implement their flexible, high-performance on-board information processing functions. In order to accommodate task changes on-orbit, repair design defects, or improve system performance, it is often necessary to update file data on the spacecraft. This process typically involves sending new document data from the surface to the spacecraft and completing online reconfiguration of the document data in the star. Therefore, the reliable, safe and efficient satellite-ground collaborative file data on-orbit updating technology is realized, and has important significance for guaranteeing long-life and reliable operation of the spacecraft and enhancing on-orbit maintenance and upgrading capability of the spacecraft. At present, a ground station is mainly adopted to directly upload the generated FPGA bit stream file to a spacecraft through a space link, after a star computer or a special configuration management unit on the spacecraft receives the data, the data is written into a configuration memory (such as PROM or Flash) of the FPGA, and then the global reconfiguration process of the FPGA is triggered to load and operate new configuration data. However, the raw configuration file is directly transmitted, so that data errors possibly generated in the transmission process cannot be effectively generated, and the error data is directly written into the configuration memory, so that the configuration failure and even the function abnormality of the FPGA can be caused, and the reliability risk caused by serious single event upset and other space environments is brought. Disclosure of Invention In view of the above-mentioned shortcomings of the prior art, an objective of the present invention is to provide a satellite-to-ground on-orbit configuration method for an antifuse FPGA, which can solve the technical problem that in the prior art, the direct transmission of an unprocessed original configuration file cannot effectively cause data errors in the transmission process, and the direct writing of the error data into a configuration memory may cause the FPGA configuration failure and even abnormal functions, resulting in serious reliability risks caused by space environments such as single event upset. In a first aspect of the embodiment of the present invention, a satellite-to-ground on-orbit configuration method for an antifuse FPGA is provided, including: S1, acquiring FPGA configuration file data; s2, performing planet ground uploading coding processing on the FPGA configuration file data to obtain ground preparation data; S3, uploading ground preparation data to the spacecraft through a space link; S4, in the spacecraft, performing data processing on ground preparation data to obtain configurable data; S5, writing the configurable data into a standby configuration area of the target FPGA; s6, carrying out integrity check on all data in the standby configuration area; S7, triggering a soft switching instruction after the integrity check, and controlling the target FPGA to switch from a main configuration area to a standby configuration area; S8, performing function verification test on the switched target FPGA to obtain a function verification test result which comprises that the function verification test passes and that the function verification test fails; S9, returning the verification result and the state information to the ground when the function verification test passes, and finishing the satellite-ground uploading and the satellite-internal file data transmission task; And S10, when the function verification test fails, a rollback instruction is sent to the target FPGA, the target FPGA is controlled to switch back to the main configuration area from the standby configuration area, and the rollback result and fault information are returned to the ground. In a second aspect of the embodiment of the invention, a satellite-to-ground on-orbit configuration system for an anti-fuse FPGA is provided, which comprises a processor and a memory; The memory stores a program or instruction executable on the processor which when executed by the processor implements the steps of the star-to-ground in-orbit configuration method for an antifuse FPGA as described in the first aspect. In a third aspect of the embodiments of the present invention, a readable storage medium is provided, where a program or an instruction is stored, where the program or the instruction implement the steps of the satellite-to-ground on-orbit configuration method for an antifuse FPGA according to the first aspect when the program or the instruction is executed by a processor. The technical scheme provided