CN-121979834-A - Leakage compensation method for 2T0C memory internal computing array

CN121979834ACN 121979834 ACN121979834 ACN 121979834ACN-121979834-A

Abstract

The invention discloses a leakage compensation method of a 2T0C memory calculation array, and belongs to the technical field of memory calculation integration. According to the invention, a 2T0C main array and a reference column driving mode is adopted, a compensation circuit is connected between RBL of the 2T0C main array and RBL of the reference column, the read voltage is dynamically regulated by the compensation circuit, calculation errors caused by a leakage effect can be effectively compensated, and the IR-Drop is balanced by applying symmetrical influence to calculation results of columns in the memory array. The invention can realize stable calculation precision in large-scale parallel calculation, remarkably improve the system performance and avoid the influence of the leakage effect on the calculation accuracy.

Inventors

WANG ZONGWEI
DING HAO
CAI YIMAO
YANG YUNFAN
LI JIYE

Assignees

北方集成电路技术创新中心(北京)有限公司
北京大学

Dates

Publication Date: 20260505
Application Date: 20260107

Claims (3)

1. The electric leakage compensation method of the 2T0C internal computing array comprises the following steps: 1) Taking one row of 2T0C memory cells in the 2T0C memory computing array as a reference row and the 2T0C memory cells in other rows as a 2T0C main array; 2) Inputting data into a 2T0C main array, saving the data sparsity of the 2T0C main array, and then inputting data with the same sparsity into a reference column; 3) And a compensation circuit is connected between the RBL of the 2T0C main array and the RBL of the reference column, and the compensation circuit applies symmetrical V read compensation to the 2T0C main array according to the voltage change of the input node of the reference column, so that the data sparseness of the reference column and the 2T0C main array is kept consistent.
2. The leakage compensation method of a 2T0C in-memory computational array of claim 1 wherein in step 3) the compensation circuit comprises a current mirror, an input sense current source and an operational amplifier, the input sense current source being configured to generate the ideal summing current based on the data sparseness of the reference column, the output of the input sense current source being connected to one input of the current mirror, the other input of the current mirror being connected to the input node of the reference column RBL, the input sense current source generating the ideal summing current when the voltage V th of the reference column drifts and being copied to the input node of the reference column RBL through the current mirror, the input node of the reference column RBL being connected to each RBL of the operational amplifier output to the main array.
3. The leakage compensation method of a 2T0C memory computational array of claim 1 wherein the 2T0C memory cells comprise read transistors and write transistors interconnected, the read transistors and write transistors being oxide semiconductor transistors or CMOS gain cells.

Description

Leakage compensation method for 2T0C memory internal computing array Technical Field The invention relates to the technical field of memory calculation integration, and provides a leakage compensation method for a 2T0C memory calculation array. Background With the widespread use of deep learning (e.g., transducer) models, there is an increasing need for computational integration techniques in processing complex models. The nonvolatile Memory (NVM), such as the resistive random access Memory (RESISTIVE RANDOM ACCESS MEMORY, RRAM) and the phase change Memory (PHASE CHANGE Memory, PCM), has high reading and writing costs, and cannot meet the requirements of fast data access and massive parallel computing, so that the nonvolatile Memory has the problem of insufficient computing capacity when dealing with complex computing tasks such as a transducer, and particularly has poor performance in application scenarios with high parallelism and low latency. In contrast, the 2T0C structure-based memory has fast read-write, low latency, and strong adaptability to fast data update, and can support efficient computation and data access. Accordingly, oxide semiconductor (Oxide Semiconductor, OS) devices or complementary metal oxide semiconductor (Complementary Metal OxideSemiconductor, CMOS) gain cells (gain cells) are becoming a research hotspot as a basis for memory architecture. The 2T 0C-based memory architecture has the potential of realizing large model deployment and acceleration, and in the memory operation with high parallelism, the leakage effect is still a key factor affecting the calculation accuracy and stability. Due to the capacitance effect and static leakage of the memory cell, small fluctuations in current can cause instability of the stored data during long-time data retention and multiple computation, thereby causing computation errors. Particularly in the environment of high parallel computing, the influence of the leakage effect is more remarkable, and the excessive refresh frequency and the limited refresh time window become main bottlenecks for limiting the storage accuracy and the operation window. In order to ensure that the accuracy of the calculation operation is preserved and to extend the available operation window, effective compensation strategies must be proposed to reduce the negative impact of the leakage effect on the calculation. On the other hand, in the high-parallelism computation, as the number of active rows in the array increases, a large number of signals still generate significant IR-Drop during transmission between rows, and the computation accuracy is affected in the high-parallelism computation, so that the computation result is deviated. Therefore, in order to effectively improve the calculation accuracy and the operation window, a double compensation technique for threshold voltage drift and IR-Drop must be developed to ensure the reliability and accuracy of the array in massive parallel calculation. Disclosure of Invention The invention provides a leakage compensation method of a 2T0C memory calculation array, which effectively compensates calculation errors caused by leakage effect by dynamically adjusting read voltage (V read). In order to achieve the above purpose, the technical scheme provided by the invention is as follows: the electric leakage compensation method of the 2T0C internal computing array comprises the following steps: 1) Taking one row of 2T0C memory cells in the 2T0C memory computing array as a reference row and the 2T0C memory cells in other rows as a 2T0C main array; 2) Inputting data into a 2T0C main array, saving the data sparsity of the 2T0C main array, and then inputting data with the same sparsity into a reference column; 3) And a compensation circuit is connected between the RBL of the 2T0C main array and the RBL of the reference column, and the compensation circuit applies a read voltage V read to the 2T0C main array for compensation according to the voltage change of the input node of the reference column, so that the data sparseness of the reference column and the 2T0C main array is kept consistent. Further, in the step 3), the compensation circuit includes a current mirror, an input sensing current source and an operational amplifier, where the input sensing current source is configured to generate an ideal summation current according to the data sparseness of the reference column, an output of the input sensing current source is connected to one input end of the current mirror, another input end of the current mirror is connected to an input node of the reference column RBL, and when the voltage V th of the reference column shifts, the input sensing current source generates the ideal summation current and copies the ideal summation current to the input node of the reference column RBL through the current mirror, and the input node of the reference column RBL is connected to each RBL of the operational amplifier output to the main array. Furth