CN-121980405-A - Wafer yield prediction method

CN121980405ACN 121980405 ACN121980405 ACN 121980405ACN-121980405-A

Abstract

The invention discloses a wafer yield prediction method which comprises the steps of (1) detecting WAT electrical parameter data of crystal grains in current wafers, marking yield labels corresponding to part of WAT electrical parameter data, finding out key WAT electrical parameters which are strongly related to yield in the current wafers, and (2) constructing a sample by the key WAT electrical parameters of the crystal grains, training a XGBoost model and using the trained XGBoost model for yield prediction of the crystal grains in the current wafers. The invention provides an automatic prediction framework with the key feature-model depth synergy, which realizes the automatic optimization from the original WAT data to the yield classification result and improves the dynamic adaptability and the reasoning efficiency of the prediction model.

Inventors

NI TIANMING
WU HAO
Nie Mu
BIAN JINGCHANG
PENG QINGSONG
LI YU
YE JING
ZHUO CHENG

Assignees

安徽工程大学

Dates

Publication Date: 20260505
Application Date: 20260114

Claims (9)

1. The wafer yield prediction method is characterized by comprising the following steps of: (1) Detecting WAT electrical parameter data of crystal grains in the current batch of wafers, marking yield labels corresponding to part of WAT electrical parameter data, and finding out key WAT electrical parameters which are strongly related to yield in the current batch of wafers; (2) And constructing a sample by using key WAT electrical parameters of the crystal grains, training the XGBoost model, and using the trained XGBoost model for predicting the yield of the crystal grains in the current batch of wafers.
2. The wafer yield prediction method as claimed in claim 1, wherein the method for selecting the key WAT electrical parameters is as follows: (11) Establishing a population, initializing the population, wherein each individual in the population represents a key WAT electrical parameter set; (12) Calculating fitness of each individual, and updating individuals with optimal fitness in the population ; (13) Detecting whether the current iteration number reaches the maximum iteration number, if so, determining that the current optimal fitness is individual The corresponding key WAT electrical parameter set is the optimal WAT electrical parameter set, if the detection result is no, the step (14) is executed; (14) For individuals in a population And (3) other individuals select the exploration strategy or the development strategy to update, and execute the step (12).
3. The wafer yield prediction method according to claim 2, wherein the code vector is extracted from WAT electrical parameter data of each die The key WAT electrical parameter data of each grain are sequentially input into a random forest classifier RF, the random forest classifier RF outputs the predicted yield of each grain, and the coding vector is calculated based on the yield label of the grain And the corresponding accuracy rate is taken as the fitness of the corresponding individual.
4. The wafer yield prediction method of claim 2, wherein each individual randomly selects either the exploration strategy or the development strategy for updating with a 50% probability.
5. The wafer yield prediction method as claimed in claim 4, wherein the updating of the code vector is performed based on a search strategy, the updated code vector The method comprises the following steps: ; Wherein, the Is an exploration factor for controlling the intensity of exploration; 、 Two D-dimensional random vectors are represented, each vector being a random number uniformly distributed over the range 0, 1.
6. The wafer yield prediction method as claimed in claim 4, wherein the updating of the code vector is performed based on a development strategy, the updated code vector The method comprises the following steps: ; Wherein, the Is a development factor for controlling the intensity of development; Representing a D-dimensional random vector, each vector being a random number uniformly distributed over the range 0, 1.
7. The wafer yield prediction method according to claim 4, wherein key WAT electrical parameter data of the die to be predicted in the current lot of wafers is input to XGBoost model, the prediction result output by XGBoost model is converted into output probability by using sigmoid function, the corresponding die yield is judged to be abnormal when the probability is larger than or equal to a set probability threshold, and the corresponding die yield is judged to be normal when the probability is smaller than the probability threshold.
8. The wafer yield prediction method according to claim 4, wherein the parameters of the XGBoost prediction model are optimized using a Bayesian super-parametric algorithm.
9. The method of claim 4, wherein the yield label is applied to a portion of dies in the current lot, the label corresponding to WAT electrical parameter data is 0 for normal dies, and the label corresponding to WAT electrical parameter data is 1 for abnormal dies.

Description

Wafer yield prediction method Technical Field The invention belongs to the technical field of wafer detection, and particularly relates to a wafer yield prediction method. Background The semiconductor industry is always the basis of advanced manufacturing worldwide, is used as a core foundation stone in the fields of high-end computing, intelligent terminals, new energy automobiles, industrial Internet and the like, has a breakthrough situation of technical evolution rate and performance, and is driving the iterative upgrading process of the modern information technology industry deeply. The semiconductor manufacturing process has extremely high process precision and full-flow cooperativity, the whole production process is divided into a wafer manufacturing stage and a wafer testing stage, the wafer manufacturing stage is subjected to a plurality of complicated production procedures, and the wafer production process diagram is shown in figure 1. The wafer test stage is divided into a wafer acceptance test (WAFER ACCEPTANCE TEST, WAT), a probe test (CP) and a final package test (FINALLY TEST, FT), and the main purpose of the test is to explore whether the wafer yield meets the requirement, and the yield is used as a core quantization index for measuring the semiconductor manufacturing efficiency and the process stability, which becomes the key of the enterprise to ensure the capacity supply and the control cost. The wafer yield not only reflects whether the design meets the expected requirement, but also reflects the stability of the manufacturing process. The WAT data is utilized to predict early yield, and timely feedback can be provided for process deviation identification, so that resource waste in the subsequent packaging test stage is avoided. Therefore, how to implement automated quality monitoring and yield prediction from massive process data has become a key requirement for ensuring line stability and reducing manufacturing overhead. However, WAT data as a prediction base stone faces challenges such as dimensional explosion, feature redundancy, complex parameter relationship and the like along with the increase of process complexity. This high dimensional isomerism makes it extremely difficult to build high precision predictive models, and traditional artificial feature screening methods are difficult to achieve efficient deployment in dynamically changing automated production lines. Currently, yield prediction studies for WAT data have focused on improvements in single feature selection algorithms (e.g., GA, PSO) or predictive models (e.g., random forests, neural networks). However, existing studies tend to ignore the synergistic relationship between feature selection and model hyper-parametric configuration. The change of the feature space can directly influence the fitting limit of the model, if the feature space and the fitting limit are regarded as isolated steps, the calculation resource waste can be caused, and the model is more easily sunk into local optimum. In addition, many models do not adequately account for wafer correlation within a lot, resulting in poor real-time and generalization capability when processing industrial large-scale data. Disclosure of Invention The present invention provides a wafer yield prediction method, which aims to solve at least one of the above problems. The invention is realized in such a way that a wafer yield prediction method is realized, and the method comprises the following steps: (1) Detecting WAT electrical parameter data of crystal grains in the current batch of wafers, marking yield labels corresponding to part of WAT electrical parameter data, and finding out key WAT electrical parameters which are strongly related to yield in the current batch of wafers; (2) And constructing a sample by using key WAT electrical parameters of the crystal grains, training the XGBoost model, and using the trained XGBoost model for predicting the yield of the crystal grains in the current batch of wafers. In the embodiment of the invention, the method for selecting the key WAT electrical parameters is specifically as follows: (11) Establishing a population, initializing the population, wherein each individual in the population represents a key WAT electrical parameter set; (12) Calculating fitness of each individual, and updating individuals with optimal fitness in the population ; (13) Detecting whether the current iteration number reaches the maximum iteration number, if so, determining that the current optimal fitness is individualThe corresponding key WAT electrical parameter set is the optimal WAT electrical parameter set, if the detection result is no, the step (14) is executed; (14) For individuals in a population And (3) other individuals select the exploration strategy or the development strategy to update, and execute the step (12). In the embodiment of the invention, the code vector is extracted from WAT electrical parameter data of each grainThe key WAT