CN-121980594-A - Memory protection and abnormality detection method, device, equipment and storage medium

CN121980594ACN 121980594 ACN121980594 ACN 121980594ACN-121980594-A

Abstract

The invention discloses a memory protection and anomaly detection method, a device, equipment and a storage medium, which relate to the technical field of information safety and comprise redefining an L field of a PMP control register in a physical memory protection mechanism of a CPU, expanding 1 bit [7] of an original L field into 2 bits [7:6], correspondingly reducing the original reserved bits [6:5] into bits [5], expanding the value range of the L bits from 0/1 to 0/1/2/3, setting the value of the L bits to 2, enabling the corresponding PMP entry to be in an unlocking state and only suitable for a Machine mode, forcedly executing read, write and execute authority control on the corresponding memory area by the CPU in the Machine mode, and setting a loaded code section without switching and an important unmodified data area into a read-only mode. The invention meets the requirement of code dynamic loading switching, and avoids the function limitation caused by authority locking.

Inventors

LV HUI
Lu Songpin
LIU HAILIANG
MA YI
XIONG WEI

Assignees

芯盛智能科技(湖南)有限公司

Dates

Publication Date: 20260505
Application Date: 20260408

Claims (5)

1. The memory protection and abnormality detection method is characterized by comprising the following steps: redefining an L field of a PMP control register in a physical memory protection mechanism of a CPU, namely expanding 1 bit [7] of an original L field into 2 bits [7:6], correspondingly reducing the original reserved bits [6:5] into bits [5], expanding the value range of the L bits from 0/1 to 0/1/2/3, setting the value of the L bits to be 2, wherein the corresponding PMP entry is in an unlocking state and is only suitable for a Machine mode, and the CPU forcedly executes read, write and authority control on the corresponding memory area in the Machine mode; Setting a loaded code section without switching and an important unmodified data area as a read-only mode, namely configuring L=2 corresponding to a PMP item, unlocking a Machine mode, setting the authority as read-only, releasing R authority, clearing W authority, namely setting R=1, W=0 and X authority according to code execution requirements; the method comprises the steps of releasing W permission of a corresponding PMP entry before switching, and clearing the W permission after switching, wherein L=2 of the corresponding PMP entry is configured before switching, namely W=1 is released to support loading and updating of codes or data; When detecting that the CPU generates abnormal access, generating abnormal access interrupt, wherein the abnormal access interrupt triggers setting the L field of the PMP control register as 2, the CPU forcedly executes write permission control on an abnormal access area in a machine mode, storing a PC pointer of a current abnormal program counter into an EPC of the abnormal program counter, and positioning a PC pointer corresponding to software faults.
2. The memory protection and anomaly detection method according to claim 1, wherein when the L-bit value of the PMP control register is 0, the corresponding PMP entry is unlocked and is only applicable to a Supervisor mode and a User mode, when the L-bit value is 1, the corresponding PMP entry is locked, and when the L-bit value is 3, the corresponding PMP entry is reserved for a subsequent expansion scene.
3. A memory protection and anomaly detection device, comprising: The physical memory protection mechanism definition module is used for redefining an L field of a PMP control register in a physical memory protection mechanism of the CPU, wherein 1 bit [7] of an original L field is expanded to 2 bits [7:6], the original reserved bits [6:5] are correspondingly reduced to bit [5], the value range of the L bit is expanded from 0/1 to 0/1/2/3, and when the value of the L bit is set to 2, the corresponding PMP item is in an unlocking state and is only suitable for a Machine mode, and the CPU forcedly executes read, write and execute authority control on the corresponding memory area in the Machine mode; The memory protection module is used for setting the loaded code section without switching and the important unmodified data area into a read-only mode, and specifically, configuring L=2 corresponding to a PMP (program execution protocol) item, unlocking the Machine mode, setting the authority into read-only mode, namely, releasing R authority, clearing W authority, namely, R=1, W=0, and setting X authority according to code execution requirements; the method comprises the steps of releasing W permission of a corresponding PMP entry before switching, and clearing the W permission after switching, wherein L=2 of the corresponding PMP entry is configured before switching, namely W=1 is released to support loading and updating of codes or data; The abnormal detection module is used for generating abnormal access interruption when detecting that the CPU generates abnormal access, the L field of the PMP control register is set to be 2, the CPU forcedly executes write permission control on an abnormal access area in a machine mode, a current abnormal program counter PC pointer is stored in an abnormal program counter EPC, and a PC pointer corresponding to software faults is positioned.
4. An electronic device, comprising a processor and a memory, wherein at least one section of program is stored in the memory, and the at least one section of program is loaded and executed by the processor to implement the memory protection and anomaly detection method according to any one of claims 1 to 2.
5. A storage medium, wherein at least one section of program is stored in the storage medium, and the at least one section of program is loaded and executed by a processor to implement the memory protection and anomaly detection method according to any one of claims 1 to 2.

Description

Memory protection and abnormality detection method, device, equipment and storage medium Technical Field The present invention relates to the field of information security technologies, and in particular, to a method, an apparatus, a device, and a storage medium for protecting a memory and detecting an abnormality. Background In the existing computer system or equipment, if the memory boundary crossing problem occurs in the bottom firmware and the driver, the code segment is easily damaged, so that the fault detection is difficult, and the breakdown of an Operating System (OS) can be caused. The existing memory management mechanism of the CPU supports setting the code segment as a read-only segment so as to realize basic code protection, but cannot meet the scene that the code needs dynamic loading switching. The current operating system generally modifies the read-write execution authority of the User mode in the Machine mode to realize the dynamic loading switching and memory protection of the User program or the dynamic library. However, for a large number of applications supporting only the Machine mode in the embedded field, and a scenario where there is an overlay application, the prior art lacks an effective memory protection scheme. As shown in FIG. 1, in the PMP mechanism of the conventional CPU, the PMP control register includes five fields, namely L (bit 7), A (bit [4:3 ]), X (bit [2 ]), W (bit [1 ]), and R (bit [0 ]), and R, W and X bits indicate whether the corresponding address area has the read, write and instruction execution rights. Wherein r=0 and w=1 indicates that the memory region is reserved. The A field is used to specify the way the address area is calculated. The L bit is used to lock the region and after locking, the writing to the corresponding control and address registers will be ignored. The locked PMP region can only be unlocked by a system reset. The state bit L (original bit 7) only supports two values, namely, when the value is 0, the PMP item is unlocked and is only suitable for the S mode and the U mode, when the value is 1, the PMP item is locked and is suitable for the Machine mode, but the authority cannot be modified in the locked state, so that a CPU running in the Machine mode cannot adapt to a code dynamic switching scene, and flexible authority control and protection on a dynamically loaded code or data segment are difficult. Disclosure of Invention The invention aims to overcome the defects of the prior art and provides a memory protection and abnormality detection method, device, equipment and storage medium, which enable a CPU to realize safe memory protection and rapid abnormality detection through flexible authority control in a Machine mode. The aim of the invention is realized by the following technical scheme: A memory protection and abnormality detection method includes: redefining an L field of a PMP control register in a physical memory protection mechanism of a CPU, namely expanding 1 bit [7] of an original L field into 2 bits [7:6], correspondingly reducing the original reserved bits [6:5] into bits [5], expanding the value range of the L bits from 0/1 to 0/1/2/3, setting the value of the L bits to be 2, wherein the corresponding PMP entry is in an unlocking state and is only suitable for a Machine mode, and the CPU forcedly executes read, write and authority control on the corresponding memory area in the Machine mode; Setting a loaded code section without switching and an important unmodified data area as a read-only mode, namely configuring L=2 corresponding to a PMP item, unlocking a Machine mode, setting the authority as read-only, releasing R authority, clearing W authority, namely setting R=1, W=0 and X authority according to code execution requirements; the method comprises the steps of releasing W permission of a corresponding PMP entry before switching, and clearing the W permission after switching, wherein L=2 of the corresponding PMP entry is configured before switching, namely W=1 is released to support loading and updating of codes or data; When detecting that the CPU generates abnormal access, generating abnormal access interrupt, wherein the abnormal access interrupt triggers setting the L field of the PMP control register as 2, the CPU forcedly executes write permission control on an abnormal access area in a machine mode, storing a PC pointer of a current abnormal program counter into an EPC of the abnormal program counter, and positioning a PC pointer corresponding to software faults. Further, when the L bit value of the PMP control register is 0, the corresponding PMP entry is unlocked and is only applicable to the super mode and the User mode, when the L bit value is 1, the corresponding PMP entry is locked, and when the L bit value is 3, the corresponding PMP entry is reserved for the subsequent expansion scene. A second aspect is a memory protection and anomaly detection device, comprising: The physical memory protection mechani