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CN-121980625-A - Privacy computing method and privacy computing system applied to core particle module

CN121980625ACN 121980625 ACN121980625 ACN 121980625ACN-121980625-A

Abstract

The invention provides a privacy computing method applied to a core module, which comprises the steps of S1, obtaining a privacy computing task, processing the privacy computing task by adopting a graph decomposition algorithm to obtain a privacy computing task graph, wherein the privacy computing task graph comprises a plurality of nodes and a plurality of edges connected with any two nodes, the nodes represent computing tasks obtained by decomposing the privacy computing task, the edges represent the dependency relationship among the computing tasks, S2, dividing each computing task into a high-sensitivity task, a medium-sensitivity task or a low-sensitivity task, S3, dividing all the high-sensitivity task, the medium-sensitivity task and the low-sensitivity task into a plurality of subtasks, distributing core particles for all the subtasks according to a preset scheduling strategy, and enabling each subtask to be independently executed on the core particles, and S4, determining the execution sequence of each computing task, so that each core particle sequentially executes all the subtasks corresponding to each computing task according to the execution sequence of each computing task.

Inventors

  • YIN CHUNSUO
  • LIU HONGWEI
  • HAO QINFEN

Assignees

  • 中国科学院计算技术研究所

Dates

Publication Date
20260505
Application Date
20251201

Claims (13)

  1. 1. A privacy computing method applied to a core module for implementing privacy computation on the core module, wherein the core module comprises a plurality of cores and a power supply module, the method comprising: Step S1, acquiring a privacy calculation task, and processing the privacy calculation task by adopting a graph decomposition algorithm to acquire a privacy calculation task graph, wherein the privacy calculation task graph comprises a plurality of nodes and a plurality of edges connected with any two nodes, the nodes represent operation tasks obtained by decomposing the privacy calculation task, and the edges represent the dependency relationship between the two connected nodes corresponding to the operation tasks; Step S2, determining the security level of each operation task according to the existing rule mapping table so as to divide each operation task into a high-sensitivity task, a medium-sensitivity task or a low-sensitivity task; S3, splitting a high-sensitivity task into a plurality of subtasks by taking a preset first value as a reference, splitting a middle-sensitivity task into a plurality of subtasks by taking a preset second value as a reference, splitting a low-sensitivity task into a plurality of subtasks by taking a preset third value as a reference, and distributing core particles for all the subtasks according to a preset scheduling strategy so that each subtask is independently executed on the core particles; And S4, determining the execution sequence of each operation task based on the dependency relationship among the operation tasks, so that each core particle sequentially executes all the subtasks corresponding to each operation task according to the execution sequence of each operation task, summarizing the calculation results of all the subtasks corresponding to the same operation task to the core particle where any one subtask is located, and transmitting the summarized calculation results of the operation task to the core particle where all the subtasks corresponding to each operation task with the dependency relationship exist, wherein all the subtasks corresponding to one operation task are executed in parallel.
  2. 2. The method of claim 1, further comprising configuring the power module to power the core in an ultra-low voltage mode, a regular voltage mode, or a high performance voltage mode such that the core operates in the ultra-low voltage mode when performing a subtask corresponding to a highly sensitive task, and such that the core operates in the regular voltage mode or the high performance voltage mode when performing a subtask corresponding to a mid-sensitive task or a low sensitive task.
  3. 3. The method of claim 2, wherein the ultra-low voltage mode has an operating voltage range of 0.4V to 0.6V, the normal voltage mode has an operating voltage of 1.0V, and the high performance voltage model has an operating voltage range of 1.1V to 1.3V.
  4. 4. The method of claim 3, further comprising configuring all of the cores to perform the subtasks at a predetermined clock cycle and causing each core to randomly introduce a time delay from within a predetermined interval of values when performing the subtasks at the predetermined clock cycle.
  5. 5. The method of claim 4, wherein the predetermined clock period is 10ns and the predetermined value interval is 2ns to 5ns.
  6. 6. The method of claim 5, further comprising configuring each of the kernels to dynamically inject noise signals of different frequency bands with respect to a preset frequency band when performing the subtask, or configuring each of the kernels to simultaneously inject noise signals of a low frequency band and a high frequency band when performing the subtask.
  7. 7. The method of claim 6, wherein the predetermined frequency range is 1HZ to 10GHZ, the low frequency range is 100MHZ to 500MHZ, and the high frequency range is 5GHZ to 10GHZ.
  8. 8. The method of claim 7, further comprising configuring each of the core particles in the core particle module to use a multi-layer composite structure of alternating copper and aluminum as a shielding layer, and providing heat dissipation channels within the shielding layer to control core particle temperature.
  9. 9. The method of claim 8, wherein the predetermined first value is 5, the predetermined second value is 3, and the predetermined third value is 2.
  10. 10. The method of claim 9, wherein the preset scheduling policy is a nearest neighbor policy, a first match policy, a best match policy, or a random match policy.
  11. 11. A privacy computing system based on the method of any of claims 1-10 for implementing privacy computation on a core module, wherein the core module comprises a plurality of cores and a power supply module, the system comprising: The task decomposition module is used for obtaining a privacy calculation task, and processing the privacy calculation task by adopting a graph decomposition algorithm to obtain a privacy calculation task graph, wherein the privacy calculation task graph comprises a plurality of nodes and a plurality of edges connected with any two nodes, the nodes represent operation tasks obtained by decomposing the privacy calculation task, and the edges represent the dependency relationship between the two connected nodes corresponding to the operation tasks; The level identification module is used for determining the security level of each operation task according to the existing rule mapping table so as to divide each operation task into a high-sensitivity task, a medium-sensitivity task or a low-sensitivity task; the slicing scheduling module is used for splitting the high-sensitivity task into a plurality of subtasks by taking a preset first value as a reference, splitting the middle-sensitivity task into a plurality of subtasks by taking a preset second value as a reference, splitting the low-sensitivity task into a plurality of subtasks by taking a preset third value as a reference, and distributing core particles for all the subtasks according to a preset scheduling strategy so that each subtask is independently executed on the core particles; The task execution module is used for determining the execution sequence of each operation task based on the dependency relationship among the operation tasks, so that each core particle sequentially executes all the subtasks corresponding to each operation task according to the execution sequence of each operation task, and after the calculation results of all the subtasks corresponding to the same operation task are summarized to the core particle where any one subtask is located, the calculation results obtained by summarizing the operation tasks are transmitted to the core particle where all the subtasks corresponding to each operation task with the dependency relationship are located, wherein all the subtasks corresponding to one operation task are executed in parallel.
  12. 12. A computer readable storage medium, having stored thereon a computer program executable by a processor to implement the steps of the method of any of claims 1-10.
  13. 13. An electronic device, comprising: one or more processors, and memory, wherein the memory is to store executable instructions; The one or more processors are configured to implement the steps of the method of any of claims 1-10 via execution of the executable instructions.

Description

Privacy computing method and privacy computing system applied to core particle module Technical Field The invention relates to the field of data security and privacy protection, in particular to a privacy computing technology in the field of data security and privacy protection, and more particularly relates to a privacy computing method and a privacy computing system applied to a core module. Background In recent years, with the increasing demands for data security and privacy protection, privacy computing technology has entered a stage of rapid development. However, existing privacy calculations still face many challenges in practical applications. For example, the complexity of privacy computation is generally high, the execution efficiency is difficult to meet the requirement of a large-scale scene, and meanwhile, the overall security is greatly compromised because the privacy computation is easily threatened by side channel attack. These problems make it difficult to achieve efficient and secure offloading of private computing tasks on traditional computing platforms. The core fraction computing architecture provides a new idea for solving the problems. The core particle level computing architecture is a core particle computing platform formed by different functional modules such as a computing core particle, a storage core particle, an IO core particle and the like, and a plurality of core particles are efficiently integrated in the same system through an advanced integrated packaging technology. The architecture can significantly improve the overall performance and computational power supply of the computing platform. While core-level computing architectures can effectively address the problems faced by computing platforms, core-level computing architectures still suffer from the following deficiencies in handling privacy computing tasks. First, high energy consumption and safety requirements are difficult to be compatible. Privacy calculations typically involve complex and intensive computational processes. Such as the execution of the multiparty secure computing (MPC) protocol, such operations consume significant hardware resources, often resulting in high computing power consumption. However, the conventional task scheduling strategy lacks dynamic adaptation capability, and cannot reasonably allocate resources according to the sensitivity level of the task calculated by different privacy. Specifically, for highly sensitive tasks with higher computing resource demands, the existing scheduling strategies often bring excessive energy consumption redundancy, while for low sensitive tasks with lower computing resource demands, privacy information leakage is easily caused by insufficient security. Second, physical layer security is not sufficient. Traditional static protection means (such as a fixed voltage power supply mode) are very fragile when the side channel attack is handled, and key information is easy to analyze by an attacker through capturing power consumption characteristics, so that privacy disclosure risks are caused. Furthermore, the power consumption characteristics tend to be further amplified when privacy computation tasks are performed cumulatively on a single die. For example, in the key generation phase, the power consumption curve of the core is extremely easy to capture by an external side channel analysis means, so that key privacy data is cracked by an attacker. Third, there is a lack of fine-grained dynamic scheduling mechanisms. Current scheduling schemes mostly focus on macro-level resource allocation and management, but fail to achieve flexible and fine scheduling for core-level resources. In the scenario of multi-task parallel execution, the difference requirements of energy consumption and safety among tasks cannot be considered, so that the balance between energy efficiency and safety is difficult to achieve. In summary, in the prior art, there are generally problems that it is difficult to combine high energy consumption and security requirements, physical layer security protection is insufficient, and a fine-granularity dynamic scheduling mechanism is missing when a privacy computing task is executed on a core-granularity architecture. It should be noted that, the present background art is only for describing the relevant information of the present invention to facilitate understanding of the technical solution of the present invention, but does not mean that the relevant information is necessarily prior art. Where there is no evidence that related information has been disclosed prior to the filing date of the present application, the related information should not be considered prior art. Disclosure of Invention It is therefore an object of the present invention to overcome the above-mentioned drawbacks of the prior art and to provide a privacy computing method and a privacy computing system applied to a core module. The aim of the invention is achieved by the followin