CN-121981028-A - Time sequence circuit node characteristic characterization system construction method and identification method

CN121981028ACN 121981028 ACN121981028 ACN 121981028ACN-121981028-A

Abstract

The invention provides a time sequence circuit node characteristic characterization system construction method which comprises the steps of S1, obtaining a time sequence circuit RTL code, synthesizing into a gate-level netlist and text description of each node, S2, obtaining a fine-tuning large language model, S3, constructing a node characteristic fusion module, S4, constructing a circuit construction module, S4, constructing a circuit diagram with the node in the gate-level netlist as a node and a directed edge in the gate-level netlist as a connecting line, and taking the node characteristic representation of the node as the node characteristic of the node in the circuit diagram, S5, obtaining a graph neural network, performing end-to-end training on the graph neural network by adopting the circuit diagram in the step S4 until convergence, S6, constructing the time sequence circuit node characteristic characterization system by using a circuit synthesis tool, the fine-tuning large language model, the node characteristic fusion module, the circuit construction module and the converged graph neural network.

Inventors

Mu Jianan
WANG MINGJUN
LI HUAWEI
YE JING
LIU ZIZHEN

Assignees

中国科学院计算技术研究所

Dates

Publication Date: 20260505
Application Date: 20251211

Claims (10)

1. A method for constructing a sequential circuit node characterization system for generating a corresponding gate level netlist from a sequential circuit RTL code and generating a textual description of each node based on the corresponding gate level netlist, the method comprising: S1, acquiring a timing circuit RTL code, synthesizing the RTL code into a gate-level netlist by using a circuit synthesis tool, and analyzing a synthesis log, a mapping file and a standard database in the circuit synthesis tool to obtain text description of each node in the gate-level netlist; S2, acquiring a fine-tuning large language model, wherein the fine-tuning large language model is used for generating high-dimensional semantic embedding of each node in the gate-level netlist; S3, constructing a node feature fusion module, wherein the node feature fusion module is used for splicing high-dimensional semantics of each node obtained by the trimmed large language model and structural features of the node in a gate-level netlist, and obtaining enhanced feature representation of the node after dimension reduction processing; S4, constructing a circuit construction module, wherein the circuit construction module is used for constructing a circuit diagram which takes a node in the gate-level netlist as a node and a directed edge in the gate-level netlist as a connecting line, and taking the enhancement characteristic of the node as the node characteristic of the node in the circuit diagram; S5, acquiring a graph neural network, and performing end-to-end training on the graph neural network by adopting the circuit diagram in the step S4 until convergence; s6, constructing a time sequence circuit node characteristic characterization system by using a circuit comprehensive tool, the trimmed large language model, a node characteristic fusion module, a circuit construction module and the converged graph neural network.
2. The method for constructing a sequential circuit node characterization system according to claim 1, wherein in step S1, a textual description of each node in the gate level netlist is obtained by: analyzing the synthesis log and the mapping file in the circuit synthesis tool to establish a mapping of register nodes in the RTL code and DFF nodes in the gate level netlist to construct a text description of each DFF node in the gate level netlist; a textual description of each common logical gate node in the gate-level netlist is constructed based on a standard database.
3. The method of claim 2, wherein analyzing the comprehensive log and the mapping file of the circuit comprehensive tool obtains information corresponding to each DFF node, namely node name, self function semantics, always block, trigger edge, reset mode and input/output port context information corresponding to the RTL code, and concatenating the information corresponding to each DFF node into normalized DFF node text description.
4. The method for constructing the time sequence circuit node characteristic characterization system according to claim 3, wherein the standard database is analyzed to obtain the information corresponding to each common logic gate node, namely the self logic function, port information and experimental parameters, and the normalized text description of the common logic gate node at the information splicing position corresponding to each common logic gate node.
5. The method for constructing a sequential circuit node characterization system according to claim 4, wherein in the step S2, the fine tuning large language model is obtained by: Acquiring any general large language model; And (3) taking the generated node text description as a prompt word, taking each node in the gate-level netlist processed in the step (S1) as an input, and taking the text characteristic representation of the node as an output fine tuning large language model until the large language model can generate the text description corresponding to each node according to the gate-level netlist.
6. The method according to claim 5, wherein the second-to-last layer of the large language model is embedded as a high-dimensional semantic embedding of the input node.
7. The method for constructing a sequential circuit node characterization system according to claim 6, wherein in step S3, an adaptive aggregation mechanism, a two-stage sequential propagation mechanism, and a local or global alignment loss are used to perform end-to-end training on a graph neural network, wherein: the self-adaptive aggregation mechanism refers to dynamically adjusting an aggregation mode according to node characteristics in the training process of the graph neural network; The connection-side timing propagation mechanism refers to the propagation of an analog signal from a circuit input along a connection of the circuit; the local alignment loss is the loss between the predicted result and the actual result of the prediction task of the graph neural network; The global alignment penalty is the alignment penalty between the gate-level netlist and the RTL code.
8. A method for characterizing a sequential circuit node, the method comprising: t1, acquiring a timing circuit RTL code to be identified, and synthesizing the RTL code into a gate-level netlist by adopting a circuit synthesis tool; T2, obtaining the text description of each node in the gate-level netlist obtained in the step T1 by using the time sequence circuit node characteristic characterization system constructed by the method as claimed in any one of claims 1-7.
9. A computer readable storage medium, having stored thereon a computer program executable by a processor to implement the steps of the method of any one of claims 1-7, 8.
10. An electronic device, comprising: one or more processors, and memory, wherein the memory is to store executable instructions; The one or more processors are configured to implement the steps of the method of any one of claims 1-7, 8 via execution of the executable instructions.

Description

Time sequence circuit node characteristic characterization system construction method and identification method Technical Field The invention relates to the technical field of Electronic Design Automation (EDA) and artificial intelligence intersection, in particular to a multi-mode (structural information and semantic information) fused integrated circuit time sequence required circuit representation learning technology, in particular to a scheme for improving the characterization capability of gate-level netlist nodes (particularly D-type trigger DFF nodes) by utilizing a large language model (LLM, large Language Model) and a graph neural network in a cooperative manner, and more particularly relates to a time sequence circuit node characterization system construction method and a time sequence circuit node characterization method. Background With the rapid growth in integrated circuit scale, circuit representation learning is becoming increasingly important in EDA. Under the prior art, the circuit representation learning method is mainly divided into two main categories: the first type is a circuit learning method based on a graph neural network (Graph Neural Networks, GNNs) that represents a circuit gate level netlist as a graph structure, learning the characteristics of logic gates or flip-flops through messaging between nodes and edges. However, when the circuit scale increases (especially, a sequential circuit including thousands to thousands of gates and flip-flops), the structured information simply relying on GNN often has a problem of rapid degradation of performance, and it is difficult to accurately predict key parameters such as a switching activity rate (toggle rate) and a timing arrival time (ARRIVAL TIME) of each node. The second category is circuit analysis methods based on language models (Large Language Models, LLMs) and in recent years, some research has begun to attempt to use pre-trained language models to understand Register Transfer Level (RTL) code to obtain high-level functional descriptions or design intent. Although the method has remarkable advantages in the aspect of understanding the whole function of the circuit, the detailed connection line and the behavior of the gate-level circuit are difficult to accurately grasp by relying on LLM only because of the abstract level difference between the RTL code and the gate-level netlist. From the above, it can be seen that the single use of GNN or LLM cannot simultaneously compromise the fine structure and semantic understanding of large-scale circuits. It should be noted that, the present background art is only for describing the relevant information of the present invention to facilitate understanding of the technical solution of the present invention, but does not mean that the relevant information is necessarily prior art. Where there is no evidence that related information has been disclosed prior to the filing date of the present application, the related information should not be considered prior art. Disclosure of Invention It is therefore an object of the present invention to overcome the above-mentioned drawbacks of the prior art and to provide a new method for constructing a sequential circuit node characterization system. According to the first aspect of the invention, a time sequence circuit node characteristic characterization system construction method is provided, the time sequence circuit node characteristic characterization system is used for generating a corresponding gate level netlist according to time sequence circuit RTL codes and generating text description of each node based on the corresponding gate level netlist, the method comprises the steps of S1, acquiring the time sequence circuit RTL codes, synthesizing the RTL codes into the gate level netlist by using a circuit synthesis tool, analyzing a synthesis log and a mapping file and a standard database in the circuit synthesis tool to obtain text description of each node in the gate level netlist, S2, acquiring a fine-tuning large language model, using the fine-tuning large language model to generate high-dimensional semantic embedding of each node in the gate level netlist, S3, constructing a node characteristic fusion module, using the high-dimensional semantic embedding of each node obtained by the fine-tuning large language model and the node in the gate level netlist, obtaining enhanced characteristic representation of the node after dimension reduction processing, S4, constructing a circuit construction module, using the node in the gate level netlist as a node, using a circuit graph with a side in the gate level as a node, and using a circuit graph as a training diagram, and a step of a node graph, and a step of constructing a neural network, and a training network, and using the node graph as a characteristic graph. Preferably, the textual description of each node in the gate-level netlist is obtained by parsing a synthesis log and a mapping file in a