CN-121981029-A - Sequential circuit hybrid fault simulation method and system

CN121981029ACN 121981029 ACN121981029 ACN 121981029ACN-121981029-A

Abstract

S1, obtaining a circuit netlist to be simulated, identifying strong communication components in the circuit netlist, and marking the strong communication components meeting the constraint conditions of a preset small-scale strong communication loop; S2, simulating a plurality of periods of the marked circuit netlist to be simulated, wherein the simulation is carried out in each simulation period, S21, code compiling is carried out on the marked strong communication components to enable each marked strong communication component to be fused into a compiling node, compiling simulation is carried out on each compiling node until the state converges, topology is updated, the output of each compiling node is transmitted to other areas in the circuit netlist as an event, S22, the other areas except the compiling node are used as event driving nodes, and the rest circuits are simulated and the circuit state is updated in an event scheduling mode.

Inventors

LI WENJIE
WANG MINGJUN
LI HUAWEI
YE JING
Chao Zhiteng
Mu Jianan

Assignees

中国科学院计算技术研究所

Dates

Publication Date: 20260505
Application Date: 20251211

Claims (10)

1. A sequential circuit hybrid fault simulation method for simulating a sequential circuit fault coverage by injecting a fault point into a sequential circuit, the method comprising: S1, obtaining a circuit netlist to be simulated, identifying strong communication components in the circuit netlist, and marking the strong communication components meeting the constraint conditions of a preset small-scale strong communication loop; S2, carrying out simulation on the marked circuit netlist to be simulated for a plurality of periods, wherein the simulation is carried out in each simulation period: S21, coding the marked strong communication components to enable each marked strong communication component to be fused into a coding node, coding simulation is carried out on each coding node until the state converges, the topology is updated, and the output of each coding node is transmitted to other areas in the circuit netlist as an event; s22, taking other areas except the compiling node as event-driven nodes, simulating a residual circuit by adopting an event scheduling mode, and updating the circuit state.
2. The hybrid fault simulation method of claim 1, wherein in step S1, all strong connected components in the circuit netlist to be simulated are identified by using the Tarjan method or the Kosaraju method.
3. The timing circuit hybrid fault simulation method according to claim 1, wherein the preset small-scale strong communication loop constraint condition is: The number of the DFFs included is 1 or two; The total number of logic gates is less than or equal to the threshold.
4. A hybrid fault simulation method for a sequential circuit according to claim 3, wherein said threshold is 10.
5. The hybrid fault simulation method of claim 4, wherein the step S21 includes: s211, performing loop analysis to determine an input/output interface, an internal trigger and a combination logic structure, and analyzing a topology generation calculation sequence; S212, generating an instruction sequence based on the analysis of the step S211, wherein the instruction sequence comprises an initialization instruction, an iterative computation instruction, a convergence check instruction and an output write-back instruction, the initialization instruction is used for reading input and states, the iterative computation instruction is used for updating internal signals, the convergence check instruction is used for comparing new and old states, and the output write-back instruction is used for writing back the output.
6. The hybrid fault simulation method of claim 5, wherein the step S21 further comprises: an independent injection function is generated for each fault point to enable fault injection through function calls.
7. The method of claim 6, wherein the instruction code is in the form of a three-address code.
8. A sequential circuit hybrid fault simulation system based on the method of any of claims 1-7, the system comprising: The circuit preprocessing module is used for receiving the circuit netlist to be simulated, identifying strong communication components in the circuit netlist, and marking the strong communication components meeting the constraint conditions of the preset small-scale strong communication loop; the code compiling simulation module is used for carrying out code compiling on the marked strong communication components so that each marked strong communication component is fused into a compiling node, carrying out compiling simulation on each compiling node until the state converges, updating the topology and transmitting the output of each compiling node as an event to other areas in the circuit netlist; The event-driven simulation module is used for taking other areas except the compiling node as event-driven nodes, simulating a residual circuit in an event scheduling mode and updating the state of the circuit; and the simulation result processing module is used for outputting a simulation report and fault coverage rate.
9. A computer readable storage medium, having stored thereon a computer program executable by a processor to implement the steps of the method of any of claims 1-7.
10. An electronic device, comprising: one or more processors, and memory, wherein the memory is to store executable instructions; The one or more processors are configured to implement the steps of the method of any of claims 1-7 via execution of the executable instructions.

Description

Sequential circuit hybrid fault simulation method and system Technical Field The invention relates to the technical field of integrated circuit design automation (EDA) technology and functional safety (Functional Safety), in particular to the field of sequential logic circuit fault simulation, and more particularly to a sequential circuit hybrid fault simulation method and system. Background Simulation of sequential circuits is a critical step in ensuring circuit design success, performance compliance, and cost effectiveness. In existing integrated circuit designs, sequential circuits place higher demands on simulation due to the presence of flip-flops (DFFs), registers, and complex feedback loops. Particularly, with the continuous improvement of functional safety requirements in safety critical fields such as automotive electronics, aerospace and the like, the standard requirements such as ISO 26262 and the like carry out a large number of fault simulations to ensure sufficient diagnosis coverage. In order to meet the functional safety standards of ISO 26262 and the like, large-scale fault simulation needs to be carried out on the target circuit so as to verify whether the target circuit can keep correctness and meet the coverage rate requirements when various faults occur. Particularly, for meeting the high security level requirements of automobile electronics or aerospace electronics, large-scale fault injection and simulation are required to be carried out on a gate-level netlist so as to obtain higher fault coverage rate. In the prior art, fault simulation of a sequential circuit can be divided into two major categories, namely 'compiling (Compiled) simulation' and 'Event-Driven (Event-Driven) simulation'. The compiled simulation usually pre-processes a circuit, and converts a logic function into directly executable machine code through a compiler, so that processing of combinational logic is accelerated. This has the advantage that the scheduler does not need to be frequently called for waveform update, but for sequential circuits comprising a feedback loop and a large number of Flip-flops (DFFs), compiled simulations may occupy too much memory for reasons of state explosion etc. and lack flexibility in facing complex loops. The event-driven simulation triggers the subsequent simulation process according to the circuit signal change (event), so that the flexibility is higher, and the event-driven simulation is widely applied to combined circuits. However, for large-scale sequential circuits, because there are many dependency relationships between feedback and registers, event scheduling is too frequent, and it is still difficult to effectively cope with the worst-case large-scale simulation requirement, resulting in high time loss. It follows that there are certain problems with both compiled and event driven simulations. How to effectively combine the respective advantages of the compiling simulation and the event driven simulation to reduce simulation redundancy and realize rapid fault simulation on a large-scale gate-level netlist becomes a common concern of the industry and academia. It should be noted that, the present background art is only for describing the relevant information of the present invention to facilitate understanding of the technical solution of the present invention, but does not mean that the relevant information is necessarily prior art. Where there is no evidence that related information has been disclosed prior to the filing date of the present application, the related information should not be considered prior art. Disclosure of Invention Therefore, an object of the present invention is to overcome the above-mentioned drawbacks of the prior art, and to provide a method and a system for hybrid fault simulation of a sequential circuit. The invention aims at realizing the following technical scheme: According to the first aspect of the invention, a time sequence circuit mixed fault simulation method is provided and used for simulating time sequence circuit fault coverage rate by injecting fault points into a time sequence circuit, and the method comprises the steps of S1, obtaining a circuit netlist to be simulated, identifying strong communication components in the circuit netlist, marking the strong communication components meeting preset small-scale strong communication loop constraint conditions, S2, carrying out simulation on the marked circuit netlist to be simulated for a plurality of periods, S21, carrying out code compiling on the marked strong communication components to enable each marked strong communication component to be fused into a compiling node, carrying out compiling simulation on each compiling node until the state converges, updating topology, transmitting the output of each compiling node to other areas in the circuit netlist as events, S22, taking the other areas except the compiling node as event driving nodes, and adopting an event scheduling mode to s