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CN-121981031-A - Modeling and simulation method of dynamic random access memory

CN121981031ACN 121981031 ACN121981031 ACN 121981031ACN-121981031-A

Abstract

The application relates to a modeling and simulation method of a dynamic random access memory. The method comprises the steps of loading transistors and interconnection parameters from a process technology parameter database based on target process nodes designated by users, supporting non-standard process node modeling through an interpolation algorithm, conducting top-down organization modeling on a dynamic random access memory by adopting a hierarchical structure, introducing H-shaped wiring network description addresses and data signal distribution, conducting design space exploration on key physical parameters such as word line segmentation numbers, bit line segmentation numbers and column multiplexing degrees to generate various physical implementation schemes, precisely calculating delay, power consumption and area by utilizing an analysis model at a circuit level, integrating specific time sequence parameters and refresh power consumption assessment of the dynamic random access memory, and finally selecting an organization scheme with optimal comprehensive performance according to multi-target optimization criteria. The application can rapidly and accurately evaluate different architecture schemes in early design stage, and provides effective support for architecture optimization of the dynamic random access memory.

Inventors

  • ZHOU PENG
  • FU CHAO
  • LIU SIYUAN

Assignees

  • 绍芯实验室

Dates

Publication Date
20260505
Application Date
20251222

Claims (10)

  1. 1. A modeling and simulation method of a dynamic random access memory is characterized by comprising the following steps: Step one, the parameter loading and processing are carried out, Based on a target process node input by a user, acquiring parameters of a transistor and an interconnection line from a process technical parameter database, and adopting a linear interpolation algorithm to process parameters of a non-standard process node; Step two, modeling the hierarchical structure, Decomposing and instantiating the dynamic random access memory model into hierarchical structures such as a unified cache access unit, a memory bank, a memory array block, a memory sub-array and the like in a top-down mode, and carrying out signal organization modeling by adopting an H-shaped wiring network; Step three, the design space is explored, Intelligent traversal and combination evaluation are carried out on key physical organization parameters (such as word line division number, bit line division number, column multiplexing degree and the like) to generate various physical implementation schemes; Step four, analyzing and calculating circuit-level indexes, Based on the parameters loaded in the step 1, adopting a resistor-capacitor time constant model and a Holovitz time delay model to perform analytical calculation and bottom-up accumulation on the time delay, dynamic power consumption, static leakage power consumption and physical area of all the hierarchical structure components; step five, multi-objective optimization selection, And selecting a physical organization scheme with the comprehensive optimal performance, power consumption and area from the results of the design space exploration according to the optimization target weight set by the user.
  2. 2. A simulation method according to claim 1, wherein in the parameter loading and processing step, the process node for deriving parameters using a linear interpolation algorithm includes, but is not limited to, an intermediate process node between two known process nodes.
  3. 3. The method according to claim 1, wherein in the hierarchical modeling step, the memory bank layer performs balanced distribution and convergence of address signals and data signals among the plurality of memory array blocks by modeling the H-type wiring network, and takes the delay and power consumption contributions of the H-type wiring network into account as a total index.
  4. 4. The method of claim 1, wherein in the design space exploration step, key physical organization parameters of the intelligent traversal include at least word line division number, bit line division number and column multiplexing degree, and complete performance, power consumption and area calculation is executed once for each combination.
  5. 5. The method of claim 1, wherein in the circuit level indicator analysis and calculation step, the delay calculation is performed by precisely summing and accumulating delays of all components including a row decoding delay, a word line delay, a bit line sensing delay, and a data input/output delay on a critical path.
  6. 6. The method of claim 1, wherein the delay computation model further integrates computation of timing parameters specific to the DRAM, the timing parameters including row-to-column command delay, row access strobe delay, and precharge delay.
  7. 7. The method of claim 1, wherein the power consumption calculation model includes not only accumulation of dynamic power consumption and static leakage power consumption, but also accurate calculation of refresh operation power consumption overhead specific to the dynamic random access memory.
  8. 8. The simulation method of claim 7, wherein the power consumption calculation model is capable of distinguishing between different power consumption characteristics in a page-on state and a page-off state, and modeling and evaluating the power consumption characteristics, respectively.
  9. 9. The method of claim 1, further comprising evaluating a three-dimensional stacked architecture, wherein the circuit level indicator resolution calculation step integrates through-silicon-via introduced latency, power consumption, and area overhead.
  10. 10. The simulation method according to any one of claims 1 to 9, further comprising a result visualization and comparison analysis step, wherein the simulation results of different physical organization schemes in performance, power consumption, area and key time sequence parameter dimensions are output uniformly, and visual comparison among multiple schemes is realized through a two-dimensional or three-dimensional chart form so as to assist a user in making design decisions.

Description

Modeling and simulation method of dynamic random access memory Technical Field The application relates to the field of integrated circuit design and electronic design automation, in particular to a modeling and simulation method of a dynamic random access memory. Background With the continuous evolution of the advanced process, the degree of dependence on a memory system in chip design is increasingly enhanced, the memory system has become one of key factors restricting overall computing performance and energy efficiency, and in modern processor architecture, a memory not only bears functions of data temporary storage and quick access, but also directly influences the effective throughput rate of a processor in an organization mode, physical implementation and access time sequence. In the performance dimension, memory access latency and bandwidth limitations significantly limit instruction execution efficiency, and particularly in a memory intensive application scenario, the performance penalty incurred by cache misses may exceed 50% of the overall performance, severely impacting system response capability. In the power consumption dimension, as the process node is continuously reduced to deep submicron or even nanometer, the leakage current of the transistor is obviously increased, the static leakage power consumption in the memory array shows a rapid rising trend, and meanwhile, the memory system gradually becomes one of main sources of the power consumption of the chip due to frequent memory access, refreshing operation and dynamic power consumption caused by long-distance interconnection, and in the area dimension, the memory generally occupies a larger layout proportion in the chip, and the area constraint not only directly affects the manufacturing cost of the chip, but also further indirectly affects the access delay and the power consumption by increasing the interconnection length and the load capacitance. The performance, the power consumption and the area have a high coupling relation, and the optimization of any dimension often has adverse effects on other dimensions, so that a complex and high-dimensional design space is formed, and the word line and bit line organization mode, the array division strategy, the multiplexing structure, the hierarchical architecture configuration and other factors of the storage system can have significant influence on the finally realized comprehensive index, so that a designer is difficult to accurately balance by experience. In the conventional chip design process, accurate evaluation of the memory system usually depends on detailed circuit level simulation or layout level analysis, and the evaluation means often needs to be performed after the register transmission level design is completed even in the physical implementation stage, once the performance, power consumption or area index cannot meet the design requirement at this stage, the design process is greatly retracted by modifying the architecture level, the design period and development cost are increased, compared with the coarse-grained estimation method adopted in the early stage of the design, although the calculation speed is higher, the influence of the process parameters, the interconnection characteristic and the specific time sequence behavior of the memory is often ignored, the prediction error is larger, and the reliable basis is difficult to provide for the key architecture decision. For the related art, the inventor considers that the prior art still lacks an effective method capable of realizing rapid performance, power consumption and area comprehensive prediction while ensuring evaluation precision in the early design stage of a storage system, and is difficult to support systematic exploration of various storage configurations and physical organization schemes, and how to efficiently and accurately model and evaluate different storage system architectures in the early design stage becomes an important technical problem for restricting chip design efficiency and success rate. Disclosure of Invention In order to solve the technical problem of how to efficiently and accurately model and evaluate different storage system architectures in early design, the application provides a modeling and simulation method of a dynamic random access memory. The modeling and simulation method of the dynamic random access memory provided by the application adopts the following technical scheme: A modeling and simulation method of a dynamic random access memory comprises the following steps: Step one, the parameter loading and processing are carried out, Based on a target process node input by a user, acquiring parameters of a transistor and an interconnection line from a process technical parameter database, and adopting a linear interpolation algorithm to process parameters of a non-standard process node; Step two, modeling the hierarchical structure, Decomposing and instantiating the dynamic random access