CN-121981032-A - RRAM-based vector retrieval chip verification method, device, equipment and medium

CN121981032ACN 121981032 ACN121981032 ACN 121981032ACN-121981032-A

Abstract

The embodiment of the invention discloses a verification method, a device, equipment and a medium of a vector retrieval chip based on RRAM (remote radio access control), wherein the verification method comprises the steps of inputting a first test vector into a preset RRAM simulation model to obtain a plurality of operation results output by the RRAM simulation model, sending a first conductance adjustment instruction to the preset simulation RRAM model for each operation result if the operation result is not in a preset first interval, returning to execute the operation of inputting the first test vector into the preset RRAM simulation model until each operation result output by the preset RRAM simulation model is in a preset target interval, and comparing the conductance state change condition of the preset RRAM simulation model in the simulation test process with a conductance control parameter value in a logic control circuit of the chip to be verified so as to perform functional verification on the logic control circuit. By adopting the technical scheme, the reliability of the verification result is effectively improved.

Inventors

ZHANG JUNFENG
ZHAO LIMING

Assignees

北京忆元科技有限公司

Dates

Publication Date: 20260505
Application Date: 20251225

Claims (10)

1. A method for verifying a vector retrieval chip based on a variable resistance memory RRAM, comprising: Inputting a first test vector into a preset RRAM simulation model to obtain a plurality of operation results output by the RRAM simulation model, wherein the preset RRAM simulation model is built based on simulation configuration data, and the simulation configuration data comprise the structure of the RRAM, the array size, the clock frequency, the conversion precision of a digital-to-analog converter DAC and an analog-to-digital converter ADC and the bus bit width; For each operation result, if the operation result is not in a preset first interval, a first conductance regulating instruction is sent to the preset simulation RRAM model, and the operation of inputting a first test vector to the preset simulation RRAM model is executed in a return mode until each operation result output by the preset simulation RRAM model is in a preset target interval, wherein the first conductance regulating instruction comprises a Set instruction or a Reset instruction, and the first conductance regulating instruction is used for controlling the preset simulation RRAM model to update a conductance value; and comparing the conductivity state change condition of the preset RRAM simulation model in the simulation test process with the conductivity control parameter value in the logic control circuit of the chip to be verified, so as to perform functional verification on the logic control circuit, wherein the conductivity state change condition comprises the number of times of conductivity adjustment and the conductivity change state.
2. The method according to claim 1, wherein the method further comprises: And if the operation results are all in the preset first interval, comparing the conductivity state change condition of the preset RRAM simulation model in the simulation test process with the conductivity control parameter value in the logic control circuit of the chip to be verified, so as to perform functional verification on the logic control circuit.
3. The method according to claim 1 or 2, wherein the preset RRAM simulation model includes: the parameter configuration module is used for receiving configuration parameter information; the integrated analog computing module is used for converting the first test vector into an analog voltage signal after receiving the first test vector, performing multiply-accumulate operation on the analog voltage signal and the conductance value, and converting the obtained operation result into digital quantity; and the integrated conductance regulating module is used for analyzing the received conductance regulating instruction, and executing conductance regulating operation according to the analysis result and based on a preset voltage conductance relation table, wherein the preset voltage conductance relation table establishes a mapping relation between voltage pulses and conductance variation.
4. The method of claim 3, wherein the preset RRAM simulation model further includes: The integrated feedback adjustment module is used for adjusting the conductivity variation according to preset conductivity adjustment times and preset second intervals, so that the current RRAM simulation model can output operation results in the preset second intervals after the current RRAM simulation model is subjected to the conductivity adjustment operation of the preset conductivity adjustment times, wherein the preset conductivity adjustment times comprise first target times corresponding to the conductivity value lifting operation and second target times corresponding to the conductivity value reducing operation.
5. The method according to claim 4, wherein the method further comprises: Inputting a second test vector and a second conductance regulating instruction into the RRAM simulation model, wherein the second conductance regulating instruction comprises preset conductance regulating times and preset second intervals, and the second conductance regulating instruction is used for controlling the RRAM simulation model to output operation results in the preset second intervals after the conductance regulating operations of the preset conductance regulating times are carried out; and comparing the consistency of the conductance regulating times in the logic control circuit with the preset conductance regulating times, and comparing the consistency of the conductance change state in the logic control circuit with the conductance change state of the RRAM simulation model when the conductance regulating operation is executed according to a second conductance regulating instruction so as to perform functional verification on the logic control circuit.
6. The method of claim 1, wherein prior to inputting the first test vector to the preset RRAM simulation model, the method further comprises: Initializing and configuring the preset RRAM simulation model through a logic control circuit of the chip to be verified, wherein parameters of the initializing and configuring comprise the row number, the column number, clock frequency parameters, DAC conversion precision and ADC conversion precision of the RRAM array of the chip to be verified; And inputting a conductance initialization Form operation instruction into the preset RRAM simulation model to control the preset RRAM simulation model to load an initial conductance value.
7. An apparatus for verifying a vector search chip based on RRAM, comprising: the simulation operation module is used for inputting a first test vector into a preset RRAM simulation model to obtain a plurality of operation results output by the RRAM simulation model, wherein the preset RRAM simulation model is built based on simulation configuration data, and the simulation configuration data comprise the structure, the array size, the clock frequency, a digital-to-analog converter DAC, the conversion precision of the analog-to-digital converter ADC and the bus bit width of the RRAM; The conductance regulating module is used for sending a first conductance regulating instruction to the preset simulation RRAM model for each operation result if the operation result is not in a preset first interval, and returning to execute the operation of inputting a first test vector to the preset simulation RRAM model until each operation result output by the preset simulation RRAM model is in a preset target interval, wherein the first conductance regulating instruction comprises a Set instruction or a Reset instruction, and the first conductance regulating instruction is used for controlling the preset simulation RRAM model to update a conductance value; And the first function verification module is used for comparing the conductivity state change condition of the preset RRAM simulation model in the simulation test process with the conductivity control parameter value in the logic control circuit of the chip to be verified so as to perform function verification on the logic control circuit, wherein the conductivity state change condition comprises the times of conductivity adjustment and the conductivity change state.
8. The apparatus of claim 7, wherein the apparatus further comprises: The test module is used for inputting a second test vector and a second conductance regulating instruction into the RRAM simulation model, wherein the second conductance regulating instruction comprises preset conductance regulating times and preset second intervals, and the second conductance regulating instruction is used for controlling the RRAM simulation model to output operation results in the preset second intervals after the conductance regulating operations of the preset conductance regulating times are carried out; And the second function verification module is used for comparing the consistency of the conductance adjustment times in the logic control circuit with the preset conductance adjustment times, and comparing the consistency of the conductance change state in the logic control circuit with the conductance change state of the RRAM simulation model when the conductance adjustment operation is executed according to a second conductance adjustment instruction so as to perform function verification on the logic control circuit.
9. An electronic device, the electronic device comprising: One or more processors; storage means for storing one or more programs, When the one or more programs are executed by the one or more processors, the one or more processors implement the method for verifying a variable resistance memory RRAM-based vector retrieval chip as recited in any one of claims 1-6.
10. A computer-readable storage medium, on which a computer program is stored, characterized in that the program, when executed by a processor, implements a verification method of a variable-resistance memory RRAM-based vector retrieval chip as recited in any one of claims 1 to 6.

Description

RRAM-based vector retrieval chip verification method, device, equipment and medium Technical Field The embodiment of the invention relates to the technical field of integrated circuit verification, in particular to a verification method, a device, equipment and a medium of a vector retrieval chip based on RRAM. Background RRAM (RESISTIVE RANDOM ACCESS MEMORY, variable resistance memory) is an emerging nonvolatile memory, and has been widely focused on the fields of vector retrieval, neural network acceleration and the like due to the potential of integration. However, in actual operation, the RRAM chip involves complex actions such as analog-to-Analog Conversion (DAC), analog-to-Digital Conversion (ADC), conductance multiply-accumulate (DAC), conductance adjustment (e.g., form operation (conductance initialization), set (setting) and Reset (Reset)), and the verification of the RRAM vector search chip faces many challenges, including on one hand, the characteristics of programming volatility, parameter discreteness, etc. of the RRAM device, and the conventional fixed model is difficult to accurately simulate the actual operation state of the RRAM device, and on the other hand, the chip design involves the requirements of the operation precision of the DAC and the ADC, flexible configuration of the array scale, etc. in the chip design, the conventional verification method lacks unified parameterized adaptation capability, resulting in long verification period and low precision, and is difficult to meet the verification requirements in complex scenes. Disclosure of Invention The embodiment of the invention provides a verification method, a device, equipment and a medium of a vector retrieval chip based on RRAM, which are used for overcoming the defects of shortening the verification period of the vector retrieval chip and improving the verification precision. In a first aspect, the present invention provides a method for verifying a vector search chip based on RRAM, where the method includes: Inputting a first test vector into a preset RRAM simulation model to obtain a plurality of operation results output by the RRAM simulation model, wherein the preset RRAM simulation model is built based on simulation configuration data, and the simulation configuration data comprise the structure, the array size, the clock frequency, a digital-to-analog converter DAC, the conversion precision of the analog-to-digital converter ADC and the bus bit width of the RRAM; For each operation result, if the operation result is not in a preset first interval, a first conductance regulating instruction is sent to a preset simulation RRAM model, and the operation of inputting a first test vector to the preset simulation RRAM model is returned to be executed until each operation result output by the preset simulation RRAM model is in a preset target interval, wherein the first conductance regulating instruction comprises a Set instruction or a Reset instruction, and the first conductance regulating instruction is used for controlling the preset simulation RRAM model to update a conductance value; And comparing the consistency of the conductivity state change condition of the preset RRAM simulation model in the simulation test process with the conductivity control parameter value in the logic control circuit of the chip to be verified so as to perform functional verification on the logic control circuit, wherein the conductivity state change condition comprises the number of times of conductivity adjustment and the conductivity change state. Optionally, the method provided by the embodiment of the invention further includes: If all operation results output by the preset RRAM simulation model are in a preset first interval, consistency comparison is carried out on the conductivity state change condition of the preset RRAM simulation model in the simulation test process and the conductivity control parameter value in the logic control circuit of the chip to be verified, so that functional verification is carried out on the logic control circuit. Optionally, the preset RRAM simulation model includes: the parameter configuration module is used for receiving configuration parameter information; The integrated analog calculation module is used for converting the first test vector into an analog voltage signal after receiving the first test vector, performing multiply-accumulate operation on the analog voltage signal and the conductance value, and converting the obtained operation result into digital quantity; and the integrated conductance regulating module is used for analyzing the received conductance regulating instruction, and executing conductance regulating operation according to the analysis result and based on a preset voltage conductance relation table, wherein the preset voltage conductance relation table establishes a mapping relation between voltage pulses and the conductance variation. Optionally, presetting the RRAM simulation m