CN-121981036-A - Time sequence circuit fault simulation method and system

CN121981036ACN 121981036 ACN121981036 ACN 121981036ACN-121981036-A

Abstract

The invention provides a time sequence circuit fault simulation method which is used for simulating a time sequence circuit fault coverage rate by injecting fault points into a time sequence circuit, and comprises the steps of S1, obtaining a circuit netlist to be simulated, identifying whether a strong communication component exists in the circuit netlist to be simulated, if the circuit to be simulated only comprises a simple loop, executing step S2, if the circuit to be simulated comprises a complex strong communication component, executing step S3, adopting a compiling simulation simple loop circuit, realizing state updating and fault point injection through an instruction sequence, S3, adopting a preset total incidence analysis method to calculate node total incidence in the circuit comprising the complex strong communication component, taking a node with the minimum total incidence as an entry node to hierarchically expand the circuit, S4, injecting the fault points into the circuit comprising the complex strong communication component and simulating, wherein a preset lazy event transmission strategy is adopted to manage event scheduling in the simulation process, and S5, outputting a simulation report and the fault coverage rate.

Inventors

LI WENJIE
WANG MINGJUN
LI HUAWEI
YE JING
Chao Zhiteng
Mu Jianan

Assignees

中国科学院计算技术研究所

Dates

Publication Date: 20260505
Application Date: 20251211

Claims (10)

1. A sequential circuit fault simulation method for simulating a sequential circuit fault coverage by injecting a fault point into a sequential circuit, the method comprising: S1, acquiring a circuit netlist to be simulated, identifying whether a strong communication component exists in the circuit netlist, if the circuit to be simulated only comprises a simple loop, executing a step S2, if the circuit to be simulated comprises a complex strong communication component, and executing a step S3; s2, adopting a compiling type simulation simple loop circuit, and realizing state updating and fault point injection through an instruction sequence; S3, calculating the total input degree of nodes in the circuit containing the complex strong communication components by adopting a preset total input degree analysis method, and taking the node with the minimum total input degree as an entry node to hierarchically spread the circuit; S4, injecting fault points into a circuit containing complex strong communication components and simulating, wherein event scheduling is managed by adopting a preset lazy event propagation strategy in the simulation process; S5, outputting a simulation report and fault coverage rate.
2. A time-series circuit fault simulation method according to claim 1, characterized in that in said step S1, all strongly connected components in the circuit netlist to be simulated are identified using the Tarjan method or Kosaraju method.
3. The method for simulating time-series circuit faults according to claim 1, wherein the preset total input degree analysis method is as follows: Wherein the method comprises the steps of Representing nodes Is characterized in that the self-entering degree of the steel wire is equal to that of the steel wire, Is a node Is provided with a set of precursor nodes of (c), Representing nodes Precursor node of (a) Is the degree of penetration of the model (C).
4. A time-series circuit fault simulation method according to claim 3, wherein in said step S3, a node having the smallest total penetration is selected as an entry node, and an input edge is cut off at the entry node to be hierarchically spread.
5. The method of claim 4, wherein for each node based on a preset lazy event propagation strategy: a list of lazy events is maintained, wherein the list of lazy events is used to record predictions or updates that may occur at a future time and if the upstream state of a node is a predicted value, no event is dispatched to the current node.
6. A method of time sequential circuit failure simulation according to claim 5, wherein if an upstream state prediction error of a node is confirmed or a true value is indeed changed, an event is dispatched to the node to trigger the current node to update and the corresponding lazy event record is cleared.
7. The method according to claim 6, wherein in the step S3, the circuit is developed by layering: for each node, calculating the sum of the self-entering degree and the entering degree of the precursor node to obtain the total entering degree; Selecting a node with the smallest total incidence as an entry node; The ingress node input edges are cut off and other nodes are assigned to different levels according to dependencies to develop the circuit layer by layer.
8. A sequential circuit failure simulation system based on the method of any of claims 1-7, the system comprising: The circuit preprocessing module is used for receiving the circuit netlist to be simulated and identifying whether the circuit netlist has a strong communication component or not; the simple loop simulation module is used for simulating a simple loop circuit by adopting compiling, and realizing state updating and fault point injection through an instruction sequence; The complex circuit simulation module is used for simulating a circuit containing complex strong communication components and is configured to calculate node total penetration in the circuit containing complex strong communication components by adopting a preset total penetration analysis method, take a node with the minimum total penetration as an entrance node to hierarchically spread the circuit, and inject fault points into the circuit containing complex strong communication components for simulation, wherein a preset lazy event propagation strategy is adopted to manage event scheduling in the simulation process; and the simulation result processing module is used for outputting a simulation report and fault coverage rate.
9. A computer readable storage medium, having stored thereon a computer program executable by a processor to implement the steps of the method of any of claims 1-7.
10. An electronic device, comprising: one or more processors, and memory, wherein the memory is to store executable instructions; The one or more processors are configured to implement the steps of the method of any of claims 1-7 via execution of the executable instructions.

Description

Time sequence circuit fault simulation method and system Technical Field The invention relates to a circuit simulation technology in electronic design automation, in particular to a simulation technology of strong communication components in a time sequence circuit, and more particularly relates to a time sequence circuit fault simulation method and system. Background Simulation of sequential circuits is a critical step in ensuring circuit design success, performance compliance, and cost effectiveness. In existing integrated circuit designs, sequential circuits place higher demands on simulation due to the presence of flip-flops (DFFs), registers, and complex feedback loops. Particularly, with the continuous improvement of functional safety requirements in safety critical fields such as automotive electronics, aerospace and the like, the standard requirements such as ISO 26262 and the like carry out a large number of fault simulations to ensure sufficient diagnosis coverage. In order to meet the functional safety standards of ISO 26262 and the like, large-scale fault simulation needs to be carried out on the target circuit so as to verify whether the target circuit can keep correctness and meet the coverage rate requirements when various faults occur. However, in the prior art, when performing fault simulation on a large-scale sequential circuit, the following bottlenecks are mainly encountered: (1) Cyclic dependencies (Feedback Loops) the sequential logic contains a large number of strongly connected components (strongly connected component, SCC structures) between the flip-flops, which can lead to repeated iterative computations in the same region, significantly degrading simulation efficiency. (2) Event redundancy, namely, in the traditional event driven simulation, once a certain node generates prediction or state change, the update of the associated node is triggered, and if the change is false prediction, unnecessary repeated scheduling is caused. The dependence problem of the feedback loop in the time sequence circuit can lead the states among multiple periods to be tightly coupled, and the calculated amount of fault simulation is obviously increased. According to the existing research, common thinking and corresponding problems of the time sequence circuit fault simulation in the prior art include: (1) Event-driven simulation, namely triggering calculation only when the signal changes, and being suitable for a scene with sparse signal switching. However, in circuits that contain a large number of loops and complex feedback, the number of event scheduling times may increase, thereby affecting overall performance. (2) Parallel mode simulation PARALLEL PATTERN accelerates parallel processing of multiple input stimulus patterns using bit-parallel mode. However, due to the inter-cycle dependence of the timing loop, complete parallelism is difficult, and when error prediction exists, the calculation results of a plurality of cycles still need to be modified in a retrospective way. (3) The compiling simulation is that the circuit is converted into a code or instruction sequence which can be directly executed, so that the acceleration can be brought to the combination logic part, but the problems of memory expansion and redundant compiling are faced on a large-scale time sequence loop. (4) Prediction execution and other hybrid approaches attempt to make predictions over multiple cycles, but require extensive rollback again once the prediction is incorrect, introducing additional overhead. It follows that the presence of a Strong Connected Component (SCC) makes it difficult for these methods in the prior art to compromise efficiency and accuracy. Thus, there is a need for deep optimization for SCC internals, reducing invalid scheduling and repetitive event propagation. It should be noted that, the present background art is only for describing the relevant information of the present invention to facilitate understanding of the technical solution of the present invention, but does not mean that the relevant information is necessarily prior art. Where there is no evidence that related information has been disclosed prior to the filing date of the present application, the related information should not be considered prior art. Disclosure of Invention Therefore, an object of the present invention is to overcome the above-mentioned drawbacks of the prior art, and to provide a method and a system for time-series circuit fault simulation. The invention aims at realizing the following technical scheme: According to a first aspect of the invention, a time sequence circuit fault simulation method is provided for simulating a time sequence circuit fault coverage rate by injecting fault points into a time sequence circuit, and the method comprises the steps of S1, obtaining a circuit netlist to be simulated, identifying whether the circuit to be simulated contains a strong communication component or not, if so, executing