CN-121981037-A - State machine detection device and verification platform

CN121981037ACN 121981037 ACN121981037 ACN 121981037ACN-121981037-A

Abstract

The application discloses a state machine detection device and a verification platform, and belongs to the field of digital chip design verification. The state machine detection device comprises a state machine jump checker, wherein the state machine jump checker is used for detecting real-time jump sequences of a state machine in a simulation process according to a preset jump path, generating and outputting detection results under the condition that the state machine is detected to jump according to the preset jump path, and the detection results comprise abnormal jump points and simulation time of the abnormal jump points, wherein the abnormal jump points are wrong in the simulation process, of the state machine.

Inventors

LI QIZHENG
ZHOU CHUNYI
FAN ZHEN
CHEN LEKAI

Assignees

苏州联芸科技有限公司

Dates

Publication Date: 20260505
Application Date: 20260120

Claims (10)

1. A state machine detection device is characterized by comprising a state machine jump checker; The state machine jump checker is used for detecting the real-time jump sequence of the state machine in the simulation process according to a preset jump path, and generating and outputting a detection result under the condition that the state machine is detected to jump according to the preset jump path, wherein the detection result comprises an abnormal jump point with an error in the simulation process of the state machine and the simulation time of the abnormal jump point.
2. The state machine detection apparatus of claim 1, wherein the state machine jump checker comprises a plurality of standard state machine jump checker components connected in series; the checking logic of the standard state machine jump checker component is determined by the real-time state, the expected state and the next state of the state machine; the standard state machine jump checker component is used for detecting whether the state machine jumps from an expected state to a next state if the state machine jumps under the condition that the real-time state of the state machine is detected to be the expected state; The preset jump path comprises N jump points, the expected state of an ith standard state machine jump checker component is obtained by the ith jump point in the N jump points, the next state of the ith standard state machine jump checker component is obtained by the (i+1) th jump point in the N jump points, and i is a positive integer smaller than N.
3. The state machine detection apparatus of claim 1, wherein, The preset jump path comprises a first preset jump path, wherein the first preset jump path is obtained based on the received first configuration information, and is a state machine jump path preset under a first type of test case, wherein the first type of test case is a test case for verifying that the state machine correctly executes a standard workflow; The state machine jump checker includes a plurality of first sub-checkers corresponding to a first type of test cases, The first sub-checker is configured to detect a real-time jump sequence of the state machine according to the first preset jump path, and generate and output a first detection result when detecting that the state machine does not jump according to the first preset jump path.
4. The state machine detection apparatus of claim 3, wherein, The preset jump path further comprises a second preset jump path, and the second preset jump path is obtained based on the received second configuration information; the second preset jump path is different from the first preset jump path, and is a state machine jump path preset under a second type of test cases, wherein the second type of test cases are test cases for verifying that the state machine executes an abnormal processing flow or a specific configuration scene; The state machine jump checker further comprises a plurality of second sub-checkers corresponding to a plurality of second types of test cases, wherein the second sub-checkers are used for detecting real-time jump sequences of the state machine according to the second preset jump paths under the condition that the first sub-checkers are covered or closed, and generating and outputting second detection results under the condition that the state machine jumps according to the second preset jump paths.
5. The state machine detection device according to any one of claims 1 to 4, further comprising a global statistics unit, wherein the global statistics unit is configured to count jump related information of the state machine in an entire simulation period, the jump related information includes an overall jump path of the state machine, a time point when the state machine enters a target state, a time length when the state machine stays in the target state, and a number of times the state machine enters the target state, and the target state is any one state that the state machine enters in a simulation process.
6. The state machine detection device according to claim 5, wherein the global statistics unit is further configured to output statistics information corresponding to a specified time point, where the statistics information includes jump related information counted by the global statistics unit from a simulation start time point to a specified time point, where the specified time point is a simulation end time point or the specified time point is earlier than the simulation end time point.
7. The state machine detection device according to claim 5, further comprising a positioning aid for acquiring real-time jump information of the state machine in a simulation process through the communication interface, and positioning a real-time jump state of the state machine and a simulation time point corresponding to the real-time jump state through the real-time jump information.
8. The apparatus of claim 7, wherein the real-time jump information collected by the positioning aid comprises digital state information of the state machine, the digital state information comprises a numerical value corresponding to a target state, and the positioning aid is further configured to perform enumeration type conversion processing on the digital state information to obtain text state information of the state machine, and output the text state information to a simulation report.
9. The state machine detection device of claim 7, wherein, in the case where the state machine detection device includes a positioning aid, a global statistics and a state machine skip checker, the positioning aid is generated based on basic information of a state machine, the global statistics is generated based on basic information of the state machine, and the state machine skip checker is generated based on basic information of the state machine, wherein the basic information of the state machine includes a name of the state machine, a bit width of the state machine, a plurality of states included in the state machine, and a value corresponding to each of the plurality of states.
10. The verification platform is characterized by comprising a verification environment component and a chip to be tested, wherein the verification environment component comprises the state machine detection device according to any one of claims 1-9, the chip to be tested comprises a state machine, and the state machine detection device is in communication connection with the state machine.

Description

State machine detection device and verification platform Technical Field The application belongs to the field of digital chip design verification, and particularly relates to a state machine detection device and a verification platform. Background In the design of digital circuit chips, a state machine often plays a role of a command center, converts complex time sequence logic into a clear state, and jumps in different states under certain trigger conditions, so that the tightness of the logic and the certainty of behaviors are ensured, and a reliable operation basis is provided for the operation of the digital circuit chips. Therefore, detection of the state machine is particularly important in order to avoid the situation that the whole chip is deadlocked and even unexpected security holes occur due to illegal jump of the state machine. In the related art, the detection of the state machine generally gives the next state of the state machine according to the real-time jump condition of the circuit, and then compares the next state with the actual jump state of the circuit, so as to monitor whether the next state of the jump of the state machine is reasonable or not and monitor the jump rationality from point to point. However, if the jump condition is wrong in the actual simulation, it cannot be detected whether the jump of the state machine is performed according to the jump sequence expected by the design, and it is difficult to accurately monitor whether the overall jump path of the state machine is reasonable, and there is a problem that the accuracy of the state machine detection device in detecting the state machine is insufficient. Disclosure of Invention The embodiment of the application provides a state machine detection device and a verification platform, which can solve the problem of insufficient accuracy of the state machine detection device in the related art. In a first aspect, an embodiment of the present application provides a state machine detection apparatus, including a state machine jump checker; The state machine jump checker is used for detecting the real-time jump sequence of the state machine in the simulation process according to the preset jump path, and generating and outputting a detection result under the condition that the state machine is detected to jump according to the preset jump path, wherein the detection result comprises an abnormal jump point and the simulation time of the abnormal jump point, which are wrong in the simulation process, of the state machine. In a second aspect, an embodiment of the present application provides a verification platform, including a verification environment component and a chip to be tested, where the verification environment component includes a state machine detection device according to the first aspect, and the chip to be tested includes a state machine, and the state machine detection device is connected with the state machine. The state machine detection device comprises a state machine jump checker, wherein the state machine jump checker is used for detecting real-time jump sequences of the state machine in the simulation process according to a preset jump path, and generating and outputting detection results under the condition that the state machine is detected to jump according to the preset jump path, wherein the detection results comprise abnormal jump points and simulation time of the abnormal jump points, which are wrong in the simulation process, of the state machine. In this way, the state machine jump checker is utilized in the state machine detection device to detect the real-time jump sequence of the state machine in the simulation process according to the preset jump path, so that whether the state machine can jump according to the preset jump path can be detected, the rationality of the whole jump path of the state machine is detected, and the accuracy of the state machine detection device in detecting the state machine is improved. Drawings FIG. 1 is a schematic diagram of a state machine detection device according to some embodiments of the present application; FIG. 2 is a schematic diagram of a state machine detection device according to some embodiments of the present application; FIG. 3 is a schematic diagram of a state machine detection device according to some embodiments of the present application; FIG. 4 is a schematic diagram of a state machine detection device according to some embodiments of the present application; FIG. 5 is a schematic diagram of a verification platform provided by some embodiments of the application; fig. 6 is a schematic flow chart diagram of a state machine verification method according to some embodiments of the present application. Reference numerals illustrate: 10-state machine detection device, 100-state machine jump checker, 110-standard state machine jump checker component, 200-global statistics, 300-positioning aid, 500-verification platform, 510-verification environment com