CN-121981039-A - Static time sequence analysis-based circuit burr optimization method and device, electronic equipment and storage medium

CN121981039ACN 121981039 ACN121981039 ACN 121981039ACN-121981039-A

Abstract

The application relates to the technical field of integrated circuit design, in particular to a static time sequence analysis-based circuit burr optimization method, a static time sequence analysis-based circuit burr optimization device, electronic equipment and a storage medium, wherein the static time sequence analysis-based circuit burr optimization method directly analyzes and balances data path time delay, accurately balances multi-path time delay of an input node of the same device on the premise of maintaining time sequence convergence, can effectively inhibit competition conditions, and reduces occurrence probability and amplitude of burrs from sources, thereby reducing dynamic power consumption caused by the static time sequence analysis; further, through being embedded in the physical design and the signing tool chain, data conversion and transmission among multiple tools are avoided, the flow is obviously simplified, the error risk is reduced, the optimization period is shortened, the optimization can be dynamically implemented according to the design stage, and the efficiency and the reliability of chip design are integrally improved.

Inventors

GAO PENGPENG
WANG FU
Cao tengfei
XU XIAOYONG
WANG YAN

Assignees

此芯科技集团有限公司

Dates

Publication Date: 20260505
Application Date: 20260407

Claims (9)

1. A method for optimizing circuit glitches based on static timing analysis, the method comprising: Acquiring static time sequence analysis data of a target circuit module, wherein the data at least comprises propagation delay information of each data signal path in the target circuit module; Determining at least one target combinational logic device to be optimized from the target circuit module based on the propagation delay information, wherein the target combinational logic device has at least one input node driven by two or more data signal paths; Determining a time delay balance operation sequence of each target combination logic device based on the optimized priority of each target combination logic device; Under the constraint of maintaining the original timing sequence convergence state of the target circuit module, sequentially executing time delay balancing operation on each target combinational logic device based on the time delay balancing operation sequence so as to reduce propagation delay differences among all data signal paths of target input nodes driving the target combinational logic device; Based on the time delay balancing operation, a change instruction for modifying the physical design of the target circuit module is generated.
2. The method of claim 1, wherein determining at least one target combinational logic device to be optimized from the target circuit module based on the propagation delay information comprises: identifying all combinational logic devices in the target circuit module based on the static timing analysis data; determining, for each of the combinational logic devices, a number of the data signal paths associated with the respective input nodes of the combinational logic device; Allocating an optimized priority to each combinational logic device by combining the total number of the data signal paths; and selecting one or more combinational logic devices as the target combinational logic devices according to the optimization priority.
3. The method of claim 1, wherein performing a delay balancing operation on a target input node of the target combinational logic device to reduce propagation delay differences between individual data signal paths to the target input node comprises: calculating propagation delay differences between data signal paths driving the same target input node based on the static timing analysis data; the propagation delay of the associated data signal path is adjusted by at least one of adjusting the logic cell layout, inserting buffers, or adjusting interconnect wiring with the goal of reducing the propagation delay difference.
4. The method of claim 1, wherein after the step of performing a delay balancing operation on the target input node of the target combinational logic device to reduce propagation delay differences between the data signal paths to the target input node, further comprising: judging whether the target combinational logic device still needs to be optimized; If so, performing time delay balancing operation on the next target combinational logic device to be optimized based on the priority level until a preset optimization completion condition is met.
5. The method of claim 1, wherein the step of sequentially performing a delay balancing operation on each of the target combinational logic devices under the constraint of maintaining an original timing closure state of the target circuit module to reduce propagation delay differences between the data signal paths driving the target input nodes of the target combinational logic devices further comprises: and updating the propagation delay information of the affected data signal paths in the static time sequence analysis data according to the result of the time delay balancing operation.
6. The method of claim 1, further comprising, after the generating a change instruction for modifying the physical design of the target circuit module based on the time delay balancing operation: Applying the change instruction to a physical design database of the target circuit module to complete a physical implementation; re-executing static time sequence analysis on the target circuit module after physical realization to obtain a time sequence analysis result; and verifying the timing sequence convergence characteristic based on the timing sequence analysis result.
7. A circuit glitch optimization apparatus based on static timing analysis, said apparatus comprising: the acquisition module is used for acquiring static time sequence analysis data of the target circuit module, wherein the data at least comprises propagation delay information of each data signal path in the target circuit module; A determining module for determining at least one target combinational logic device to be optimized from the target circuit module based on the propagation delay information, wherein the target combinational logic device has at least one input node driven by two or more data signal paths; the sequencing module is used for determining the time delay balance operation sequence of each target combination logic device based on the optimized priority of each target combination logic device; The balancing module is used for sequentially executing time delay balancing operation on each target combinational logic device based on the time delay balancing operation sequence under the constraint of maintaining the original time sequence convergence state of the target circuit module so as to reduce propagation delay difference among all data signal paths of a target input node driving the target combinational logic device; And the generating module is used for generating a change instruction for modifying the physical design of the target circuit module based on the time delay balancing operation.
8. An electronic device comprising a memory for storing a computer program and a processor that runs the computer program to cause the electronic device to perform the method of any one of claims 1 to 6.
9. A storage medium having stored therein computer program instructions which, when read and executed by a processor, perform the method of any of claims 1 to 6.

Description

Static time sequence analysis-based circuit burr optimization method and device, electronic equipment and storage medium Technical Field The present invention relates to the field of integrated circuit design technologies, and in particular, to a static timing analysis-based circuit burr optimization method and apparatus, an electronic device, and a storage medium. Background In chip design, glitches (glitches) refer to unnecessary transient transitions in the combinational logic circuit due to signal timing imbalance, which directly result in a glitch power, i.e., additional dynamic power consumption caused by the glitches. Researches show that the ineffective turnover can obviously increase the dynamic power consumption of the circuit, and the amplitude can reach more than 40%. Especially in the scene that the AI accelerator and the like need to frequently execute complex calculation, the burr problem is more prominent, not only serious power consumption waste is caused, but also electromagnetic interference (EMI) and power network IR voltage drop can be caused, and further the reliability and stability of the chip are threatened. At present, a simulation waveform analysis method based on an actual working mode is commonly adopted in the industry to perform burr identification and optimization. According to the method, a simulation waveform containing time sequence information is generated by constructing an excitation signal under a typical application scene, signal jump characteristics in the waveform are analyzed by means of an EDA tool (such as Synopsys PrimePower), a high-risk burr path is positioned, and delay balance and burr suppression are achieved by adjusting the layout of a logic unit or inserting a buffer. Although the design efficiency is improved within a certain range, the method has obvious limitations that firstly, the method is highly dependent on a specific working mode, can only optimize for a scene used by simulation, is difficult to consider the overall requirement of a multi-mode multiplexing circuit (such as an AI accelerator supporting dynamic scheduling), secondly, the method is complex in flow and long in period, and a plurality of links such as simulation, waveform analysis and multi-tool data exchange are needed, so that optimization failure is easily caused by data conversion errors, and meanwhile, the design iteration time is prolonged. Therefore, there is an urgent need for a glitch optimization method that can get rid of the dependency on the simulation of a specific working mode, can directly analyze based on the static timing characteristics of a circuit, and can be seamlessly integrated in a physical design flow, so as to realize balanced optimization of multiple working modes and significantly shorten the design period. Disclosure of Invention In view of the above, the present invention aims to provide a static timing analysis-based circuit burr optimization method and device, an electronic device, and a storage medium. In a first aspect, an embodiment of the present invention provides a method for optimizing a circuit burr based on static timing analysis, the method including: acquiring static time sequence analysis data of a target circuit module, wherein the data at least comprises propagation delay information of each data signal path in the target circuit module; determining at least one target combinational logic device to be optimized from the target circuit module based on the propagation delay information, wherein the target combinational logic device has at least one input node driven by two or more data signal paths; determining a time delay balance operation sequence of each target combination logic device based on the optimized priority of each target combination logic device; Under the constraint of maintaining the original timing sequence convergence state of the target circuit module, sequentially executing time delay balance operation on each target combinational logic device based on the time delay balance operation sequence so as to reduce propagation delay difference among all data signal paths of target input nodes of the driving target combinational logic device; Based on the time delay balancing operation, a change instruction for modifying the physical design of the target circuit module is generated. With reference to the first aspect, the step of determining at least one target combinational logic device to be optimized from the target circuit module based on the propagation delay information includes: Identifying all combinational logic devices in the target circuit module based on the static timing analysis data; Determining, for each combinational logic device, a number of data signal paths associated with respective input nodes of the combinational logic device; allocating optimized priorities to the combination logic devices by combining the number of all data signal paths; and selecting one or more combinational logic devices as the tar