CN-121981041-A - Local dynamic reconfiguration streaming method and device based on multiple dynamic region division

CN121981041ACN 121981041 ACN121981041 ACN 121981041ACN-121981041-A

Abstract

The embodiment of the application provides a local dynamic reconfiguration streaming method and device based on multiple dynamic region division. The method comprises the steps of generating a mixed netlist file according to static logic and a plurality of first dynamic logic, respectively generating a plurality of independent netlist files according to a plurality of second dynamic logic, executing a bit stream processing flow of the mixed netlist file to obtain an integral bit stream file and a plurality of first bit stream files, respectively executing the bit stream processing flow of the independent netlist files to obtain a plurality of second bit stream files, and replacing a first target file in the plurality of second bit stream files with a second target file in the plurality of first bit stream files to obtain a reconfiguration bit stream file. According to the technical scheme provided by the embodiment of the application, the flow of the previous integral region calibration is split, each dynamic region is independently processed and a corresponding bit stream is generated, so that the mutual influence among the regions is avoided, and the local bit stream reconfiguration can be realized in the subsequent use process of the FPGA.

Inventors

CAI ZHONGLIANG
WANG JUNJIE
XU XIAOLONG

Assignees

深圳市紫光同创电子股份有限公司

Dates

Publication Date: 20260505
Application Date: 20251205

Claims (10)

1. A local dynamic reconfiguration method based on multiple dynamic region partitioning, the method comprising: generating a mixed netlist file according to the static logic and the first dynamic logics, respectively generating independent netlist files according to the second dynamic logics, and respectively corresponding to the logic functions; Executing the bit stream processing flow of the mixed netlist file to obtain an overall bit stream file and a plurality of first bit stream files, wherein the first bit stream files comprise at least one of first dynamic bit stream data, first static bit stream data and first enabled reconfiguration bit stream data; Respectively executing bit stream processing flows of the independent netlist files to obtain a plurality of second bit stream files, wherein the second bit stream files comprise at least one of second dynamic bit stream data, second static bit stream data and second enabled reconfiguration bit stream data; and replacing a first target file in the plurality of second bit stream files with a second target file in the plurality of first bit stream files to obtain a reconfiguration bit stream file, wherein the reconfiguration bit stream file is used for realizing local dynamic reconfiguration of bit streams, and the first target file and the second target file correspond to the same dynamic area.
2. The method of claim 1, wherein performing the bitstream processing of the mixed netlist file results in an overall bitstream file and a plurality of first bitstream files, comprising: Analyzing the mixed netlist file, and reading logic configuration information and winding configuration information; completing a region calibration process according to a plurality of pre-stored dynamic region information, the logic configuration information and the winding configuration information; completing a frame calibration process based on a calibration result of the region calibration process, wherein the calibration result of the frame calibration process comprises a dynamic frame, a shared frame, a static frame and an enabled reconfiguration frame; After the configuration point corresponding to the enabling reconfiguration frame is configured to be 0, outputting first enabling bit stream data, and after the configuration point corresponding to the enabling reconfiguration frame is configured to be 1, outputting second enabling bit stream data, and obtaining the first enabling reconfiguration bit stream data; separating and outputting the first dynamic bit stream data according to the dynamic frame and the shared frame; separating and outputting the first static bitstream data according to the static frame and the shared frame; And generating the whole bit stream file according to the dynamic frame, the shared frame, the static frame and the enabling reconfiguration frame.
3. The method according to claim 2, wherein the performing the region calibration process according to the pre-stored plurality of dynamic region information, the logic configuration information and the winding configuration information includes: Marking the function modules in the dynamic region as dynamic function modules according to the dynamic region information; Marking the functional modules of the logic routing in the static area passing through the dynamic area as shared functional modules; And marking the function modules except the shared function module in the static area as static function modules.
4. A method according to claim 3, wherein said completing a frame calibration procedure based on the calibration result of said region calibration procedure comprises: Acquiring frame address information of the sharing function module, and determining a data frame corresponding to the frame address information of the sharing function module as the sharing frame; Acquiring frame address information of the dynamic function module, and determining data frames except the shared frame in corresponding data frames as the dynamic frame based on the frame address information of the shared function module and the frame address information of the dynamic function module; Acquiring frame address information of the static function module, and determining a data frame corresponding to the frame address information of the static function module as the static frame; And acquiring frame address information of an enabling reconfiguration function module, and determining a data frame corresponding to the frame address information of the enabling reconfiguration function module as the enabling reconfiguration frame.
5. The method of claim 2, wherein the performing the bitstream processing of the plurality of independent netlist files, respectively, results in a plurality of dynamic bitstream data, comprising: for each independent netlist file, after the configuration point corresponding to the enabling reconfiguration frame is configured to be 0, outputting third enabling bit stream data, and after the configuration point corresponding to the enabling reconfiguration frame is configured to be 1, outputting fourth enabling bit stream data, and obtaining second enabling reconfiguration bit stream data; Separating and outputting the second dynamic bit stream data according to the dynamic frame and the shared frame; and separating and outputting the second static bit stream data according to the static frame and the shared frame.
6. The method of any one of claims 1 to 5, comprising, prior to said generating a hybrid netlist file from the static logic and the plurality of first dynamic logic, and generating a plurality of independent netlist files from the plurality of second dynamic logic, respectively: Displaying the reconfigurable area; dividing a plurality of dynamic areas in the reconfigurable area, and storing dynamic area information corresponding to the dynamic areas respectively.
7. The method of claim 6, wherein the dividing the plurality of dynamic regions in the reconfigurable region comprises: The method includes the steps of obtaining marking information of a region starting point of each dynamic region, obtaining marking information of a region ending point of each dynamic region, and dividing the reconfigurable region into a plurality of dynamic regions based on the marking information of the region starting point and the marking information of the region ending point of each dynamic region.
8. The method of claim 6, wherein the dividing the plurality of dynamic regions in the reconfigurable region comprises: dividing the reconfigurable area into the dynamic areas according to the logic function realized by the reconfigurable area.
9. A localized dynamic reconfiguration device based on multiple dynamic region partitioning, the device comprising: A netlist generating unit for generating a mixed netlist file according to the static logic and a plurality of first dynamic logics, and respectively generating a plurality of independent netlist files according to a plurality of second dynamic logics, wherein the independent netlist files respectively correspond to a plurality of logic functions; a first processing unit, configured to execute a bitstream processing procedure of the mixed netlist file to obtain an overall bitstream file and a plurality of first bitstream files, where the first bitstream files include at least one of first dynamic bitstream data, first static bitstream data, and first enabled reconfiguration bitstream data; The second processing unit is used for respectively executing bit stream processing flows of the independent netlist files to obtain a plurality of second bit stream files, wherein the second bit stream files comprise at least one of second dynamic bit stream data, second static bit stream data and second enabled reconfiguration bit stream data; the bitstream reconfiguration unit is configured to replace a first target file in the plurality of second bitstream files with a second target file in the plurality of first bitstream files to obtain a reconfiguration bitstream file, where the reconfiguration bitstream file is used to implement local dynamic reconfiguration of a bitstream, and the first target file and the second target file correspond to the same dynamic area.
10. A computer readable storage medium, characterized in that the computer readable storage medium has stored therein a computer program which, when executed by a processor, implements the method of any of claims 1-8.

Description

Local dynamic reconfiguration streaming method and device based on multiple dynamic region division Technical Field The embodiment of the application relates to the technical field of programmable logic devices, in particular to a local dynamic reconfiguration bit stream method and device based on multiple dynamic region division. Background In Field-Programmable gate array (Field-Programmable GATE ARRAY, FPGA) applications, dynamic reconfiguration techniques can change part of the logic functions of the FPGA while the system is running. In the related art, the dynamic reconfiguration technology is specifically implemented by setting a dynamic reconfiguration switch GSEB, and under the condition that the dynamic reconfiguration switch is in an on state, new bit stream data can be replaced with original bit stream data in the FPGA to implement dynamic reconfiguration. However, the above technology treats all the dynamic reconfiguration areas needing to be reconfigured as a whole, but cannot implement bitstream reconfiguration for a single independent dynamic reconfiguration area, which is not flexible enough. Disclosure of Invention The embodiment of the application provides a local dynamic reconfiguration streaming method and device based on multiple dynamic region division. The embodiment of the application provides a local dynamic reconfiguration bit stream method based on multiple dynamic region division, which comprises the steps of generating a mixed netlist file according to static logic and multiple first dynamic logic, generating multiple independent netlist files according to multiple second dynamic logic, enabling the multiple independent netlist files to correspond to multiple logic functions respectively, executing bit stream processing flow of the mixed netlist file to obtain an integral bit stream file and multiple first bit stream files, wherein the first bit stream file comprises at least one of first dynamic bit stream data, first static bit stream data and first enabled reconfiguration bit stream data, respectively executing bit stream processing flow of the multiple independent netlist files to obtain multiple second bit stream files, and enabling the second bit stream files to comprise at least one of second dynamic bit stream data, second static bit stream data and second enabled reconfiguration bit stream data, enabling the first target file in the multiple second bit stream files to replace the second target file in the multiple first bit stream files to obtain a reconfiguration bit stream file, and enabling the reconfiguration bit stream file to be used for realizing the same dynamic bit stream file. In a second aspect, an embodiment of the present application provides a local dynamic bit stream reconfiguration device based on multiple dynamic region division, where the local dynamic bit stream reconfiguration device includes a netlist generating unit configured to generate a mixed netlist file according to static logic and multiple first dynamic logic, and generate multiple independent netlist files according to multiple second dynamic logic, where the multiple independent netlist files correspond to multiple logic functions, a first processing unit configured to execute a bit stream processing procedure of the mixed netlist file to obtain an overall bit stream file and multiple first bit stream files, where the first bit stream file includes at least one of first dynamic bit stream data, first static bit stream data, and first enabling bit stream data, and a second processing unit configured to execute a bit stream processing procedure of the multiple independent netlist files to obtain multiple second bit stream files, where the second bit stream files include at least one of second dynamic bit stream data, second static bit stream data, and second enabling bit stream data, and a reconfiguration unit configured to replace a first target bit stream file in the multiple second bit stream files with the first target bit stream file in the multiple second bit stream files to obtain a second bit stream file in the same as the target bit stream file. In a third aspect, an embodiment of the present application provides a computer readable storage medium, in which a computer program is stored, which when executed by a processor implements a method according to the first aspect. Compared with the related art, the technical scheme provided by the embodiment of the application has the technical effects that the whole reconfiguration region is divided according to the functional logic to obtain a plurality of independent netlist files, in the bit stream generation process, the mixed netlist files are processed, bit stream generation processes are respectively executed on the independent netlist files, the previous whole region calibration process is split, each dynamic region is independently processed and a corresponding bit stream is generated, the mutual influence among the regions is avoi