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CN-121981046-A - Method for optimizing ARINC659 bus signal integrity

CN121981046ACN 121981046 ACN121981046 ACN 121981046ACN-121981046-A

Abstract

The invention relates to the field of avionics bus signal integrity design, in particular to a method for optimizing ARINC659 bus signal integrity. The method comprises the steps of building an ARINC659 bus signal backboard framework model, optimizing a receiving and transmitting end terminating circuit structure, refining resistance parameters according to the receiving and transmitting end terminating circuit structure, refining parallel inductance parameters according to the receiving and transmitting end terminating circuit structure, refining direct current resistance parameters in a parallel inductance, optimizing a backboard terminating circuit structure, and refining series inductance parameters according to the backboard terminating structure. The method can be suitable for multi-branch circuit signal integrity optimization scenes, and the impedance consistency is improved.

Inventors

  • SUN FENGYUAN
  • HUANG XINYI
  • LI BINGKUN
  • LI RUI
  • JIANG JUNBO
  • SHEN TAO
  • ZHANG PENGFEI
  • SONG YANG

Assignees

  • 中国航空工业集团公司西安飞行自动控制研究所

Dates

Publication Date
20260505
Application Date
20251224

Claims (8)

  1. 1. A method of optimizing ARINC659 bus signal integrity, comprising: Step 1, building an ARINC659 bus signal backboard architecture model; step 2, respectively adding a function board terminating circuit structure at the receiving and transmitting ends of the function board; step 3, determining parameters of a termination circuit structure of the functional board; step 4, adding a backboard terminating circuit structure between the ARINC659 bus end and the pull-up voltage; and 5, determining parameters of the backboard terminating circuit structure.
  2. 2. The method according to claim 1, wherein the step 1 is specifically: Step 11, importing a PCB design engineering file of a functional board into model extraction software, setting PCB lamination and via parameters to ensure consistency with actual processing; step 12, obtaining an IBIS model and a connector S parameter model of a processing chip; Step 13, importing PCB design engineering files of the backboard into model extraction software, setting PCB lamination and via parameters to ensure consistency with actual processing; and 14, connecting the link S parameter model of the functional board, the link S parameter model of the backboard, the IBIS model of the processing chip and the S parameter model of the connector according to an ARINC659 bus signal backboard architecture to form an ARINC659 bus signal backboard architecture model.
  3. 3. The method of claim 2 wherein the functional board termination circuit structure of step 2 is a set of resistor and inductor parallel structures.
  4. 4. A method according to claim 3, characterized in that step 3, in particular: Step 31, using the parameter scanning function of the link simulation software tool to perform parameter scanning on the resistor and the inductor in the receiving-transmitting end termination circuit structure; And 32, after confirming the specific resistance value of the terminating resistor of the receiving and transmitting end, modifying the parallel inductance parameter by using the parameter scanning function of the link simulation software tool, scanning the inductance parameter variable, stepping by 50nH from 100nH to 1000nH, and determining the terminating inductance value.
  5. 5. The method of claim 4, wherein the step 31 is to set the resistance of the terminating resistor from 1 Ω to 10 Ω, step 1 Ω, shunt inductance from 1nH to 1000nH, step 100nH, and determine the value of the resistor in the terminating structure of the receiving end by observing the signal waveform of the receiving end of the function board.
  6. 6. The method of claim 5, wherein step 3 further comprises: and 33, after confirming the termination inductance value, maintaining the inductance value unchanged, modifying the equivalent direct current resistance of the inductance, and determining the resistance value of the direct current resistance in the inductance by combining the signal waveform.
  7. 7. The method of claim 1, wherein in step 4, the back-plane termination circuit structure is an inductive structure in series with a pull-up resistor.
  8. 8. The method according to claim 1, characterized in that step 5, in particular, is: and after confirming the specific resistance value of the pull-up resistor, modifying the series inductance parameter from 100nH to 1000nH, stepping by 50nH and determining the inductance value by combining the signal waveform by using the parameter scanning function of the link simulation software tool.

Description

Method for optimizing ARINC659 bus signal integrity Technical Field The invention relates to the field of avionics bus signal integrity design, in particular to a method for optimizing ARINC659 bus signal integrity. Background The ARINC659 bus is used as an aviation bus to ensure high safety and high reliability of signal transmission in a time triggering mode. The bus is a multi-node serial communication bus, is mainly used for data information transmission among a plurality of online replaceable modules, and is widely applied to a fly pipe system. The ARINC659 bus is realized as a multi-branch circuit, and the signal of the receiving end of the middle branch in the multi-branch circuit is usually poor, which is mainly due to the fact that the receiving end positioned in the middle has larger reflection, and the reflected signals of a plurality of receiving ends can be repeatedly oscillated and overlapped in the middle branch, so that the transmission waveform is distorted and deteriorated, and the signal integrity is affected. To ameliorate this effect it is often necessary to add a matching resistor at each branch to achieve reduced reflection. Disclosure of Invention The invention aims to: a method of optimizing ARINC659 bus signal integrity is provided to improve ARINC659 bus signal integrity by optimizing the impedance and waveform of the branch circuit. The technical scheme is as follows: A method of optimizing ARINC659 bus signal integrity, comprising: Step 1, building an ARINC659 bus signal backboard architecture model; step 2, respectively adding a function board terminating circuit structure at the receiving and transmitting ends of the function board; step 3, determining parameters of a termination circuit structure of the functional board; step 4, adding a backboard terminating circuit structure between the ARINC659 bus end and the pull-up voltage; and 5, determining parameters of the backboard terminating circuit structure. Further, the step1 is specifically as follows: Step 11, importing a PCB design engineering file of a functional board into model extraction software, setting PCB lamination and via parameters to ensure consistency with actual processing; step 12, obtaining an IBIS model and a connector S parameter model of a processing chip; Step 13, importing PCB design engineering files of the backboard into model extraction software, setting PCB lamination and via parameters to ensure consistency with actual processing; And 14, connecting the link S parameter model of the functional board, the link S parameter model of the backboard, the IBIS model of the processing chip and the S parameter model of the connector according to an ARINC659 bus signal backboard architecture to form an ARINC659 bus signal backboard architecture model. 3. The method of claim 2, wherein the functional board termination circuit structure of step 2 is a set of parallel resistor and inductor structures. Further, step 3, specifically, is: Step 31, using the parameter scanning function of the link simulation software tool to perform parameter scanning on the resistor and the inductor in the receiving-transmitting end termination circuit structure; And 32, after confirming the specific resistance value of the terminating resistor of the receiving and transmitting end, modifying the parallel inductance parameter by using the parameter scanning function of the link simulation software tool, scanning the inductance parameter variable, stepping by 50nH from 100nH to 1000nH, and determining the terminating inductance value. Further, step 31 is specifically to set the resistance of the terminating resistor from 1Ω to 10Ω, step 1Ω, and step 100nH for the parallel inductor from 1nH to 1000nH, and determine the value of the resistor in the terminating structure of the receiving end by observing the signal waveform of the receiving end of the function board. Further, step 3 further includes: and 33, after confirming the termination inductance value, maintaining the inductance value unchanged, modifying the equivalent direct current resistance of the inductance, and determining the resistance value of the direct current resistance in the inductance by combining the signal waveform. Further, in step4, the back-plane termination circuit structure is an inductance structure connected in series with the pull-up resistor. Further, step 5, specifically, is: and after confirming the specific resistance value of the pull-up resistor, modifying the series inductance parameter from 100nH to 1000nH, stepping by 50nH and determining the inductance value by combining the signal waveform by using the parameter scanning function of the link simulation software tool. The beneficial effects are that: The invention relates to the field of avionics bus signal integrity design, in particular to a termination structure and a design method for optimizing ARINC659 bus signal integrity. Compared with the current ARINC659 bus signal backboard architec