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CN-121981062-A - Integrated circuit layout wiring design method and system

CN121981062ACN 121981062 ACN121981062 ACN 121981062ACN-121981062-A

Abstract

The invention relates to the field of integrated circuit design, and provides a method and a system for designing layout and wiring of an integrated circuit; the method comprises the steps of firstly obtaining an integrated circuit layout, identifying a target area in the layout, inquiring a preset deviation table according to the target area, obtaining a corresponding resistance correction coefficient and a capacitance correction coefficient, calculating a first cost based on wiring length, congestion degree and time sequence delay for each candidate wiring path, calculating a compensation cost by combining the correction coefficients, taking the sum of the first cost and the compensation cost as the total cost, selecting a wiring path according to the total cost, and if the selected path passes through the target area, carrying out line width and/or line spacing adjustment on line segments in the area.

Inventors

  • CHENG SIRONG

Assignees

  • 深圳市荣和美科技有限公司

Dates

Publication Date
20260505
Application Date
20260126

Claims (10)

  1. 1. An integrated circuit layout wiring design method, the method comprising: Acquiring an integrated circuit layout and identifying a target area in the layout; determining a resistance correction coefficient and a capacitance correction coefficient corresponding to the target area according to the target area and a preset deviation table; Calculating a first cost of each candidate wiring path based on wiring length, congestion degree and time delay, and calculating a compensation cost according to the resistance correction coefficient and the capacitance correction coefficient; And selecting a wiring path according to the total cost, and if the selected wiring path passes through the target area, executing adjustment on a line segment in the target area in the wiring path.
  2. 2. The integrated circuit layout and wiring design method according to claim 1, wherein the identifying the target area in the layout comprises: Extracting two side edge coordinate sequences of an interconnection line from the integrated circuit layout; Comparing the edge coordinate sequence with a preset standard interconnection line edge model, and calculating the maximum deviation distance between the actual edge and the standard edge; and when the maximum deviation distance is larger than a preset distance, marking the area where the interconnection line is located as the target area.
  3. 3. The integrated circuit layout and wiring design method according to claim 1, wherein the identifying the target area in the layout comprises: Extracting two side edge coordinate sequences of an interconnection line from the integrated circuit layout; Performing Fourier transformation on the edge coordinate sequence to obtain a fluctuation amplitude and a fluctuation period; and when the fluctuation amplitude is larger than a first fluctuation threshold value and the fluctuation period is smaller than a second fluctuation threshold value, determining the area where the interconnection line is located as the target area.
  4. 4. A method of designing an integrated circuit layout according to any one of claims 1 to 3, wherein the predetermined deviation table is established according to: Establishing a three-dimensional geometric model one by one for a plurality of parameter combinations including line width and line distance, and running electromagnetic field finite element simulation to obtain a simulation resistance value and a simulation capacitance value; substituting the three-dimensional geometric model into a preset empirical formula to obtain an empirical resistance value and an empirical capacitance value; taking the ratio of the simulation resistance value to the empirical resistance value as a resistance correction coefficient, and taking the ratio of the simulation capacitance value to the empirical capacitance value as a capacitance correction coefficient; And storing the resistance correction coefficient, the capacitance correction coefficient and the corresponding parameter combinations thereof into the preset deviation table.
  5. 5. The integrated circuit layout and routing design method according to claim 4, wherein calculating a first cost based on a routing length, a congestion level and a timing delay for each candidate routing path comprises: Measuring the geometric length of a candidate wiring path from a starting point to an end point, and multiplying the geometric length by a first weight coefficient to obtain a length cost component; Counting the number of grid points occupied by other wires in the wiring grid points passed by the candidate wiring paths, and multiplying the number by a second weight coefficient to obtain a congestion cost component; calculating estimated delay time of a candidate wiring path by adopting a preset delay model, and multiplying the estimated delay time by a third weight coefficient to obtain a time sequence cost component; and adding the length cost component, the congestion cost component and the time sequence cost component to obtain the first cost.
  6. 6. The method of claim 5, wherein calculating a compensation cost based on the resistance correction coefficient and the capacitance correction coefficient comprises: Calculating a correction resistor R ', a correction capacitor C ' according to the empirical resistance value R0, the empirical capacitance value C0 of the candidate wiring path, the resistance correction coefficient Kr and the capacitance correction coefficient Kc obtained from the deviation lookup table, wherein the correction resistor R ' =Kr×R0; calculating a correction delay T ' by adopting the preset delay model based on the correction resistor R ' and the correction capacitor C ', and calculating an original delay T by adopting the preset delay model based on the empirical resistor value R0 and the empirical capacitor value C0; And determining the difference between the correction delay T' and the original delay T as the compensation cost.
  7. 7. The integrated circuit layout and routing design method according to claim 1, wherein the adjustment is performed on line segments in the routing path within the target area, including line width adjustment and/or line spacing adjustment; If the resistance correction coefficient exceeds a first preset threshold value, increasing the width of a line segment in a target area according to a first proportion; the line interval adjustment comprises the step of increasing the center distance between the line segment and the adjacent line segment in the target area according to a second proportion if the capacitance correction coefficient exceeds a second preset threshold value.
  8. 8. The integrated circuit layout and routing design method according to claim 7, wherein said performing an adjustment to a line segment in the routing path that is within the target area further comprises: After the line interval adjustment is executed, the capacitance correction coefficient is recalculated, and if the recalculated capacitance correction coefficient still exceeds the second preset threshold value, the line width adjustment is executed; and after the line width adjustment is executed, recalculating the resistance correction coefficient, and executing the line spacing adjustment if the recalculated resistance correction coefficient still exceeds the first preset threshold value.
  9. 9. The integrated circuit layout design method of claim 8, further comprising: re-inquiring the preset deviation table based on the adjusted line width value and line interval value to obtain an adjusted resistance correction coefficient and a capacitance correction coefficient; Calculating an adjusted compensation cost according to the adjusted resistance correction coefficient and the adjusted capacitance correction coefficient; If the total cost after the adjustment is smaller than the total cost before the adjustment, the adjustment is reserved, and if the total cost after the adjustment is larger than or equal to the total cost before the adjustment, the adjustment is canceled, and the line width and the line spacing before the adjustment of the line segment are restored.
  10. 10. An integrated circuit layout design system, the system comprising: the acquisition and identification module is used for acquiring the integrated circuit layout and identifying a target area in the layout; the determining module is used for determining a resistance correction coefficient and a capacitance correction coefficient corresponding to the target area according to the target area and a preset deviation table; The cost calculation module is used for calculating a first cost based on the wiring length, the congestion degree and the time delay of each candidate wiring path and calculating a compensation cost according to the resistance correction coefficient and the capacitance correction coefficient; And the adjustment module is used for selecting a wiring path according to the total cost, and if the selected wiring path passes through the target area, performing adjustment on a line segment in the target area in the wiring path.

Description

Integrated circuit layout wiring design method and system Technical Field The present application relates to the field of integrated circuit design, and in particular, to a method and system for designing an integrated circuit layout and wiring. Background Under three-dimensional stacking and heterogeneous integration techniques, chip routing complexity has proliferated and conventional EDA tools face significant challenges. The problems of difficult convergence of signal timing and uneven power consumption distribution are frequent, so that the performance of a chip cannot reach the standard, and the root is the lag of a parasitic parameter extraction method. The traditional method is based on a simplified physical model and an empirical formula of a two-dimensional plane process, and the interconnection line is assumed to be in an ideal uniform form. However, in advanced processes, the cross section of the metal line shows non-rectangular non-uniformity due to process fluctuation, and the interface electrical characteristics of heterogeneous materials of the multi-layer stack are complex, which is difficult to describe with a simple model. This results in systematic deviations of the predicted values and the actual values of parasitic parameters such as resistance, capacitance, inductance, etc. The deviation directly affects the reference data of the static timing analysis and the power consumption analysis. The critical path delay, signal integrity and power consumption distribution calculated by the EDA tool are all based on the distortion parameters, so that the simulation result is seriously deviated from the real behavior of the chip. The paths meeting the requirements in the time sequence report may be delayed in an actual chip to exceed the standard and fail to reach the target frequency due to underestimation of parasitic parameters, and the areas with moderate power consumption are predicted, and the areas with high current density and difficult heat dissipation are formed due to underestimation of resistance. This deviation makes it difficult for the design team to foresee and circumvent critical issues before tape-out, ultimately leading to dual failure of chip performance and reliability. In view of the above, there is a need in the art for improvements. Disclosure of Invention The application discloses a method and a system for designing an integrated circuit layout wiring, which aim to solve the problem that in the existing integrated circuit layout wiring design, because a parasitic parameter extraction method is based on a simplified physical structure and an empirical formula, prediction deviation is caused, so that signal time sequence accuracy and power consumption distribution balance are affected, and finally the actual performance of a chip can not reach design expectations. The technical scheme of the application is as follows: in a first aspect, the present application discloses a method for designing a layout and wiring of an integrated circuit, the method comprising: Acquiring an integrated circuit layout and identifying a target area in the layout; Determining a resistance correction coefficient and a capacitance correction coefficient corresponding to the target area according to the target area and a preset deviation table; Calculating a first cost based on the wiring length, the congestion degree and the time delay of each candidate wiring path, and calculating a compensation cost according to the resistance correction coefficient and the capacitance correction coefficient; and selecting a wiring path according to the total cost, and if the selected wiring path passes through the target area, performing adjustment on a line segment in the wiring path, wherein the line segment is positioned in the target area. The target area comprises two side edge coordinate sequences of an interconnection line extracted from the integrated circuit layout, the edge coordinate sequences are compared with a preset standard interconnection line edge model, the maximum deviation distance between an actual edge and a standard edge is calculated, and when the maximum deviation distance is larger than a preset distance, the area where the interconnection line is located is marked as the target area. Further, comparing the edge coordinate sequence with a preset standard interconnection line edge model, wherein the method comprises the steps of carrying out Fourier transformation on the edge coordinate sequence to obtain fluctuation amplitude and fluctuation period, and judging the area where the interconnection line is located as the target area when the fluctuation amplitude is larger than a first fluctuation threshold value and the fluctuation period is smaller than a second fluctuation threshold value. On the basis of the above, the application further provides the preset deviation table, which is established according to the following modes that a three-dimensional geometric model is established