CN-121981066-A - Design method of chip substrate, electronic equipment and computer readable storage medium

CN121981066ACN 121981066 ACN121981066 ACN 121981066ACN-121981066-A

Abstract

The application discloses a design method of a chip substrate, electronic equipment and a computer readable storage medium, and relates to the technical field of substrate design; the method comprises the steps of obtaining specification information of an initial impedance signal wire, obtaining an impedance difference comparison table, adjusting the specification information of the initial impedance signal wire according to the impedance difference of a plurality of reference impedance signal wires before and after encapsulation in the impedance difference comparison table, obtaining adjusted specification information, and designing wiring on the initial substrate according to the adjusted specification information to obtain a chip substrate. By the design, the signal integrity is ensured.

Inventors

Xiang Yuanbiao
TONG YUMING
He Nianlong
CHEN CHANGXIONG
LI JIALIN
TANG XIAOMAN

Assignees

深圳市时创意电子股份有限公司

Dates

Publication Date: 20260505
Application Date: 20251231

Claims (10)

1. The design method of the chip substrate is characterized by comprising the following steps: Providing an initial substrate; acquiring specification information of an initial impedance signal line; Obtaining an impedance difference comparison table, wherein the impedance difference comparison table comprises impedance differences of a plurality of reference impedance signal lines before and after encapsulation; According to the impedance difference of the corresponding reference impedance signal line in the impedance difference comparison table before and after packaging, the specification information of the initial impedance signal line is adjusted to obtain adjusted specification information; and designing wiring on the initial substrate according to the adjusted specification information to obtain the chip substrate.
2. The method for designing a chip substrate according to claim 1, wherein the step of obtaining an impedance difference comparison table, wherein the impedance difference comparison table includes a plurality of preset impedance signal lines before and after the step of packaging, further includes: providing an unpackaged reference substrate, wherein a plurality of reference impedance signal wires are distributed on the unpackaged reference substrate; detecting impedance values of a plurality of reference impedance signal lines in the unpackaged reference substrate to obtain a first impedance value set; packaging the unpackaged reference substrate to obtain a packaged reference substrate; detecting impedance values of a plurality of reference impedance signal lines in the packaged reference substrate to obtain a second impedance value set; and comparing the first impedance value set with the second impedance value set to obtain the impedance difference of the reference impedance signal line before and after packaging, and summarizing to obtain an impedance difference comparison table.
3. The method according to claim 1, wherein in the step of adjusting the specification information of the initial impedance signal line according to the impedance difference of the reference impedance signal line corresponding to the impedance difference comparison table before and after packaging to obtain the adjusted specification information, adjusting the specification information of the initial impedance signal line includes adjusting at least one of a line width, a line length, a line thickness, and a differential pitch of the initial impedance signal line.
4. The method of claim 2, wherein the step of obtaining a second set of impedance values after detecting the impedance values of the plurality of reference impedance signal lines in the packaged reference substrate further comprises: Placing the packaged reference substrate in a preset environment, wherein the preset environment comprises a preset temperature; And detecting the impedance values of the plurality of reference impedance signal lines in the packaged reference substrate in a preset environment to obtain a second impedance value set.
5. The method of claim 4, wherein the predetermined environment further comprises a predetermined humidity.
6. The method for designing a chip substrate according to claim 1, wherein the step of adjusting the specification information of the initial impedance signal line according to the impedance difference of the reference impedance signal line corresponding to the impedance difference comparison table before and after packaging to obtain the adjusted specification information comprises: Compensating and correcting the initial impedance value of the initial impedance signal line according to the impedance difference of the corresponding reference impedance signal line before and after encapsulation in the impedance difference comparison table to obtain a corrected impedance value; And adjusting specification information of the initial impedance signal line according to the corrected impedance value to obtain adjusted specification information.
7. The method of designing a chip substrate according to claim 3, wherein the line width is adjusted to a range of 0.5 μm to 10 μm when the line width of the initial impedance signal line is adjusted, the differential pitch is adjusted to a range of 1 μm to 15 μm when the differential pitch of the initial impedance signal line is adjusted, and the line thickness is adjusted to a range of 0.3 μm to 5 μm when the line thickness of the initial impedance signal line is adjusted.
8. The method according to claim 2, wherein in the step of providing an unpackaged reference substrate on which a plurality of reference impedance signal lines are arranged, the number of the reference impedance signal lines of the same length and the same impedance includes at least three; And in the first and second sets of impedance values, the impedance values of the reference impedance signal lines of the same length and the same impedance are averaged.
9. An electronic device, the electronic device comprising: at least one processor, and A memory communicatively coupled to the at least one processor, wherein, The memory stores instructions executable by the at least one processor to enable the at least one processor to perform the method of designing a chip substrate according to any one of claims 1 to 8.
10. A computer-readable storage medium storing a computer program, wherein the computer program, when executed by a processor, implements the method of designing a chip substrate according to any one of claims 1 to 8.

Description

Design method of chip substrate, electronic equipment and computer readable storage medium Technical Field The present application relates to the field of substrate design technology, and in particular, to a method for designing a chip substrate, an electronic device, and a computer readable storage medium. Background As the signal rate increases, the signal integrity requirements for the signal become more stringent, and one of the means for ensuring that the signal integrity meets the protocol standards is to ensure that the impedance of the high-speed signal is continuous. However, in the wafer patch proofing process, due to the different material characteristics of the package, the impedance perceived by the chip substrate is not as uniform as the surface, so that the impedance value of the packaged chip substrate does not meet the expected requirement. Disclosure of Invention The application aims to provide a design method of a chip substrate, electronic equipment and a computer readable storage medium, which ensure the integrity of signals. The application discloses a design method of a chip substrate, which comprises the following steps: Providing an initial substrate; acquiring specification information of an initial impedance signal line; Obtaining an impedance difference comparison table, wherein the impedance difference comparison table comprises impedance differences of a plurality of reference impedance signal lines before and after encapsulation; According to the impedance difference of the corresponding reference impedance signal line in the impedance difference comparison table before and after packaging, the specification information of the initial impedance signal line is adjusted to obtain adjusted specification information; and designing wiring on the initial substrate according to the adjusted specification information to obtain the chip substrate. Optionally, the obtaining an impedance difference comparison table, where the impedance difference comparison table includes a plurality of preset impedance signal lines before the step of packaging the impedance differences between the front and rear sides of the package, further includes: providing an unpackaged reference substrate, wherein a plurality of reference impedance signal wires are distributed on the unpackaged reference substrate; detecting impedance values of a plurality of reference impedance signal lines in the unpackaged reference substrate to obtain a first impedance value set; packaging the unpackaged reference substrate to obtain a packaged reference substrate; detecting impedance values of a plurality of reference impedance signal lines in the packaged reference substrate to obtain a second impedance value set; and comparing the first impedance value set with the second impedance value set to obtain the impedance difference of the reference impedance signal line before and after packaging, and summarizing to obtain an impedance difference comparison table. Optionally, in the step of obtaining the adjusted specification information by adjusting the specification information of the initial impedance signal line according to the impedance difference of the reference impedance signal line corresponding to the impedance difference comparison table before and after packaging, the adjusting the specification information of the initial impedance signal line includes adjusting at least one of a line width, a line length, a line thickness and a differential pitch of the initial impedance signal line. Optionally, the step of obtaining the second impedance value set after detecting the impedance values of the plurality of reference impedance signal lines in the packaged reference substrate further includes: Placing the packaged reference substrate in a preset environment, wherein the preset environment comprises a preset temperature; And detecting the impedance values of the plurality of reference impedance signal lines in the packaged reference substrate in a preset environment to obtain a second impedance value set. Optionally, the preset environment further includes a preset humidity. Optionally, the step of adjusting the specification information of the initial impedance signal line according to the impedance difference of the reference impedance signal line corresponding to the impedance difference comparison table before and after packaging to obtain the adjusted specification information includes: Compensating and correcting the initial impedance value of the initial impedance signal line according to the impedance difference of the corresponding reference impedance signal line before and after encapsulation in the impedance difference comparison table to obtain a corrected impedance value; And adjusting specification information of the initial impedance signal line according to the corrected impedance value to obtain adjusted specification information. Optionally, when the line width of the initial impedance signal line is ad