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CN-121981067-A - Collaborative acceleration method for wafer-level chip design and manufacture

CN121981067ACN 121981067 ACN121981067 ACN 121981067ACN-121981067-A

Abstract

The invention belongs to the technical field of integrated circuit core particle design and manufacture, and particularly relates to a wafer-level chip design and manufacture collaborative acceleration method; the method analyzes the customizing requirement of an electronic circuit integrated system, determines the core parameters of radio frequency core particles and power core particles, prefabricates the bottom layer structures of the two types of core particles, customizes the top functional layer to construct a multi-voltage-domain power supply unit, customizes the cutting specification and the bonding pad parameters of a wafer, and adapts to direct wire bonding interconnection among the core particles. The invention solves the problems of long period and high cost of the existing full customization mode through innovations such as prefabrication and customization collaborative architecture, and the like, and realizes rapid customization and high-efficiency integration of core particles.

Inventors

  • LUO SUIXIN

Assignees

  • 广州十方尺科技有限公司

Dates

Publication Date
20260505
Application Date
20260204

Claims (10)

  1. 1. A wafer-level chip design and manufacturing collaborative acceleration method is applied to customized production of radio frequency core grains and power core grains and integration of the radio frequency core grains with other functional core grains, and is characterized by comprising the steps of analyzing customization requirements of an electronic circuit integrated system, defining a working frequency band, gain, output power level, noise coefficient and voltage level, output current range and current limiting threshold of the radio frequency core grains, prefabricating a bottom layer structure of the radio frequency core grains, wherein the bottom layer structure comprises a universal bottom layer component comprising a transistor array and a basic interconnection layer, the bottom layer structure of the prefabricated power core grains comprises a universal core module comprising a Pass transistor array, a reference voltage module, an amplifier module and a basic protection unit, customizing a top layer metal layer of the radio frequency core grains, the top layer metal layer comprises a radio frequency functional component comprising an inductor, a transformer and top layer interconnection wiring, selectively connecting target devices in the transistor array through wiring, through hole interconnection and contact hole configuration, customizing a top layer metal interconnection layer of the radio frequency core grains comprises a power supply circuit, a step-up circuit, a step-down circuit, a filter circuit, a power management circuit, a control link and a control link, and a plurality of independent power supply units are arranged in a mode that the number of the radio frequency core grains is determined according to the requirements of the wafer core grains, and the number of the interconnection chip is directly determined.
  2. 2. The method for collaborative acceleration of wafer level chip design and fabrication according to claim 1, wherein the step of pre-fabricating the bottom layer structure of the rf core includes integrating a transistor array covering device types with different gains and powers, constructing a general-purpose base interconnect network covering a core connection path between devices, depositing and routing a bottom thin metal layer of the path, and reserving connection vias with a top metal layer.
  3. 3. The method for collaborative acceleration of wafer level chip design and fabrication according to claim 1, wherein the step of prefabricating the underlying structure of the power supply core comprises integrating a multi-specification Pass transistor array, prefabricating a reference voltage module, an operational amplifier module and a base protection unit, prefabricating an underlying metal layer and a through hole array, constructing a universal interconnection node between the modules, and reserving a customized wiring interface, wherein the Pass transistor array supports power supply output with different power levels through wiring combination.
  4. 4. The wafer-level chip design and manufacturing collaborative acceleration method according to claim 1 is characterized in that the top metal layer customization step of the radio frequency core particle comprises the steps of converting a working frequency band, a gain, an output power level and a noise coefficient into top metal layer customization parameters, establishing a matching algorithm of the customization parameters and a subsequent process library to generate a preliminary scheme of top metal wiring and device size, manufacturing an inductor and a transformer on a top thick metal layer, adjusting the size and layout of the inductor and the transformer, selectively connecting target devices in a transistor array through wiring, through hole interconnection and contact hole configuration, enabling transistors to keep complete physical structures, manufacturing top interconnection wiring, and adjusting the wiring length, the corner mode and the shielding structure of the top interconnection wiring.
  5. 5. The wafer-level chip design and manufacturing collaborative acceleration method is characterized in that the top metal interconnection layer customization step of the power supply core particle comprises the steps of converting a voltage level, an output current range and a current limiting threshold value into circuit configuration parameters, determining design schemes of a feedback network, a current limiting module and a compensation module, connecting a Pass transistor array, a reference voltage module and an amplifier module through metal wiring, constructing a power supply circuit adapting to multiple voltage domains, manufacturing link wiring of current limiting control, overvoltage protection, over-temperature protection, short circuit protection and under-voltage locking, manufacturing feedback link wiring, manufacturing wiring of a power supply output interface and a control interface according to system integration requirements, and enabling interface spacing to meet circuit design rules.
  6. 6. The wafer level chip design and manufacturing collaborative acceleration method according to claim 1, wherein the wafer cutting specification determining step includes determining an aspect ratio of a core particle according to a power level of a radio frequency core particle or the number of output channels of a power core particle, positioning a critical circuit and a bonding pad area through circuit edge detection, planning a cutting path, setting a unified cutting reference and an accuracy standard, and ensuring that the sizes of core particles produced in batch are consistent.
  7. 7. The method for collaborative acceleration of wafer level chip design and fabrication according to claim 1, wherein the step of determining the parameters of the bonding pads includes determining the number, size, location and arrangement of bonding pads according to the number and type of radio frequency signal interfaces and power output interfaces, adjusting the pitch and orientation of bonding pads, supporting direct wire bonding interconnection between die, and setting uniform bonding pad packaging standards and interface definitions.
  8. 8. The wafer level chip design and manufacturing collaborative acceleration method according to claim 4 is characterized in that the top metal layer customization of the radio frequency core particle further comprises the steps of adjusting metal line width, line spacing, winding mode, layer number configuration and device size proportion, defining performance indexes of filters, couplers and transmission lines, adapting enabling logic of transistor arrays of different types and different processes, adapting customization configuration of various circuit topologies, adapting wiring constraint of metal layer process specifications of different process nodes and different integration dimensions, and adapting signal transmission in various packaging modes.
  9. 9. The wafer-level chip design and manufacturing collaborative acceleration method according to claim 5 is characterized in that the top metal interconnection layer customization of a power supply core particle further comprises the steps of constructing a linear power supply framework, a switch power supply framework, an LDO framework, a DC-DC conversion framework or a charge pump framework through metal wiring, setting resistance parameters, capacitance parameters and a topological structure of a feedback network, manufacturing a compensation circuit and a dynamic load response optimization circuit, enabling each power supply unit to realize precision synchronization and consistency control through a shared reference module or an independent configuration reference module through differentiated wiring, module combination and functional configuration of the top metal interconnection layer, reserving an enabling interface, a voltage regulating interface and a monitoring interface, and supporting independent power supply management, dynamic voltage regulation and power supply state monitoring of different heterogeneous core particles, isomorphic core particles and functional modules.
  10. 10. The collaborative acceleration method for wafer level chip design and fabrication according to any one of claims 1-9, wherein the following process steps are performed during the customization process, wherein the process design rules are followed when the bottom layer structure is prefabricated, the pitch, width and via connection status of the metal layer wiring are checked when the top layer structure is customized, and the wafer dicing and bonding pad scheme meets the packaging process requirements.

Description

Collaborative acceleration method for wafer-level chip design and manufacture Technical Field The invention belongs to the technical field of integrated circuit core particle design and manufacture, and particularly relates to a wafer-level chip design and manufacture collaborative acceleration method. Background In the development process of heterogeneous integration technology, the radio frequency core particle and the power core particle are used as key components of a heterogeneous core particle system, and the design and manufacture mode directly influences the overall efficiency of the system. In the prior art, the main stream of core design and manufacture adopts a full customization mode, the complete layout of the core needs to be redesigned according to different application scenes, and the interconnection from a bottom device to a top layer needs to be independently developed. In the mode, the inductance of the radio frequency core particle, the reference circuit of the amplifier and the power core particle, the current limiting module and the like all need to be simulated again for verification, so that the development period is long, and the quick iteration requirement of the terminal product is difficult to match. Meanwhile, each type of core particle in the full-customization mode needs to be independently manufactured into a photoetching mask, so that the cost of non-frequent expenditure is high, the wafer utilization rate is low during small-batch production, and the risk of stock waste exists. This core problem severely restricts the large-scale application and industrial development of the core technology. Based on the above-mentioned problems, there is a need for a synergistic design and manufacturing scheme for core particles that can shorten the development period and reduce the cost. Disclosure of Invention The invention aims to solve the defects in the prior art, and provides a collaborative acceleration method for designing and manufacturing a wafer-level chip, which is applied to the customized production of radio frequency core particles and power core particles and the integration of the radio frequency core particles and other functional core particles, and is characterized by comprising the steps of analyzing the customization requirement of an electronic circuit integrated system, and determining the working frequency band, gain, output power level, noise coefficient, voltage level, output current range and current limiting threshold of the radio frequency core particles; the structure comprises a base layer structure of a prefabricated radio frequency core particle, a base layer structure of the prefabricated radio frequency core particle, a top layer metal layer of the customized radio frequency core particle, a top layer metal interconnection layer of the customized radio frequency core particle, a power supply management circuit, a control link and a protection link, wherein the base layer structure comprises a general-purpose type base layer component comprising a transistor array and a basic interconnection layer, the general-purpose type base layer component comprises a Pass transistor array, a reference voltage module, an amplifier module and a basic protection unit, the base layer structure comprises a general-purpose type core module comprising a Pass transistor array, a reference voltage module, a base protection unit, the top layer metal layer comprises a radio frequency function component comprising an inductor, a transformer and a top layer interconnection wiring, the radio frequency function component is selectively connected with a target device in the transistor array through wiring, through hole interconnection and contact hole configuration, the top layer metal interconnection layer of the customized radio frequency core particle comprises a power supply circuit, a step-up step-down circuit, a filter circuit, a power supply management circuit, a control link and a protection link, a plurality of independently controllable power supply units are constructed, wafer cutting specifications are determined according to the functional requirements of the radio frequency core particle and the power supply core particle, core parameters comprising the number, size, position and arrangement mode are determined according to the inter-particle interconnection requirements, and direct wire bonding interconnection between cores is adapted. Preferably, the bottom structure prefabrication step of the radio frequency core particle comprises an integrated transistor array, a general basic interconnection network and a deposition and wiring path bottom thin metal layer, wherein the transistor array covers device types corresponding to different gains and powers, the general basic interconnection network is constructed, the basic interconnection network covers a core connection path between devices, and connection through holes with a top metal layer are reserved. Further prefe