CN-121981069-A - Method, tool and program product for optimizing time sequence consistency

CN121981069ACN 121981069 ACN121981069 ACN 121981069ACN-121981069-A

Abstract

The application discloses a method, a tool and a program product for optimizing time sequence consistency, and relates to the field of chip design. The method comprises the steps of reading time sequence data from a time sequence database of each stage, creating a violation path group corresponding to each stage based on the time sequence data, analyzing and calculating path adjustment parameters corresponding to each violation path group in different stages and time sequence difference conditions of each violation path group in different stages, indicating to adjust or indicate to enter the next flow to a target stage according to the time sequence difference conditions, entering verification of signing if the next flow is indicated to enter, and setting the path adjustment parameters to run before the target stage is implemented if the adjustment is indicated to the target stage. The method of the application improves the time sequence consistency and the accuracy of the critical path in each physical design stage, does not need to judge according to the experience of the designer, and does not have the situation of too tight constraint or too loose constraint. The iteration speed and the timing sequence convergence speed of the physical design are better accelerated, and the automation capacity of the physical design flow is improved.

Inventors

ZHANG YUE
XIAO BIN

Assignees

龙芯中科技术股份有限公司

Dates

Publication Date: 20260505
Application Date: 20251212

Claims (13)

1. A method for optimizing timing consistency, comprising: reading time sequence data from a time sequence database of each stage; creating a violation path group corresponding to each stage based on the time sequence data; analyzing and calculating to obtain path adjustment parameters corresponding to each violation path group in different stages and time sequence difference conditions of each violation path group in different stages; according to the time sequence difference condition, indicating to the target stage to adjust or indicating to enter the next flow; if the next flow is indicated, signature verification is entered, if the adjustment is indicated to the target stage, the path adjustment parameters corresponding to the target stage are set to run before the implementation of the target stage, so as to optimize the time sequence consistency.
2. The method of claim 1, wherein creating the set of violation paths corresponding to each phase based on the time series data comprises: after the wiring stage of the first physical design is finished, grouping the time sequence data of each stage according to a preset grouping strategy, and creating a corresponding violation path group for all time sequence violation paths in the time sequence data of each stage.
3. The method of claim 2, wherein grouping the timing data of each stage according to a preset grouping policy creates a corresponding set of violating paths for all timing violation paths in the timing data of each stage, comprising: In each time sequence data, all time sequence violation paths are grouped according to the names of the transmitting trigger and the capturing trigger or the module level name, and a violation path group in the corresponding stage of the time sequence data is created.
4. The method of claim 3, wherein the module hierarchy names include 1-N hierarchy names, and grouping all timing violation paths by their transmit trigger and capture trigger names or the module hierarchy names comprises: Taking the name of a transmitting trigger in the time sequence violation path as a path group starting point of a packet, taking the name of a capturing trigger as a path group end point of the packet, and creating a violation path group, wherein the violation path group comprises a plurality of time sequence violation paths; Taking the module level name of any one of the timing violation paths as a path group starting point of a packet, and taking the module level name of the capturing trigger at the same level as the module level name of any one of the emission triggers as a path group end point of the packet, wherein the higher the level number of the module level names, the fewer the number of violation path groups which can be created by all the timing violation paths, and the more the timing violation paths in each violation path group.
5. The method of claim 1 wherein analyzing and calculating path adjustment parameters corresponding to each of the set of violating paths at different stages and timing differences of each of the set of violating paths at different stages comprises: defining a violation path group corresponding to a target stage in each stage in the physical design process as a reference path group, wherein the reference path group is a violation path group corresponding to a T-th stage in the physical design process, and T is greater than 1; And comparing and analyzing the violation values corresponding to the violation paths in the reference path group with the violation values corresponding to the same violation paths in the violation path group corresponding to each stage before, and calculating to obtain the path adjustment parameters and the time sequence difference conditions corresponding to the violation paths in different stages.
6. The method of claim 5, wherein the calculating the path adjustment parameters and the timing difference for each of the violated path groups at different stages comprises: When the reference path group is a violation path group corresponding to the T-th stage, m violation paths are all provided, the violation values corresponding to the m violation paths are S 1 ,S 2 ,…,S m , the violation values corresponding to the m violation paths in the violation path group corresponding to the T-X stage are P 1 ,P 2 ,…,P m , the comparison analysis is performed to obtain that the time sequence difference of the path group between the T-X stage and the T-th stage is ΔS 1 =S 1 -P 1 ,ΔS 2 =S 2 -P 2 ,…,ΔS m =S m -P m ; Obtaining the maximum value in the time sequence difference to obtain a maximum time sequence difference value M, and when n violating path groups are in total, n maximum time sequence difference values M 1 ,M 2 ,…,M n are provided and are used as path adjustment parameters corresponding to the n violating path groups between the T-X stage and the T stage; Calculating the variance of the n maximum time sequence difference values M 1 ,M 2 ,…,M n to obtain time sequence difference variances between the T-X stage and the T stage; according to the method for comparing and analyzing the T-X stage and the T stage and calculating the time sequence difference variance, analyzing any two stages before the T stage to obtain all the time sequence difference variances; Comparing all the time sequence difference variances with a preset time sequence consistency threshold value, and obtaining the time sequence difference condition according to a comparison result.
7. The method of claim 6, wherein indicating to the target stage to adjust or to enter a next process based on the timing difference condition comprises: When the time sequence difference condition is that each time sequence difference variance is smaller than the preset time sequence consistency threshold value, the next flow is indicated; And if any time sequence difference variance is not smaller than the preset time sequence consistency threshold, indicating to the target stage to adjust, wherein n maximum time sequence difference values M 1 ,M 2 ,…,M n corresponding to the time sequence difference variance which is not smaller than the preset time sequence consistency threshold are used in the adjustment process.
8. The method of claim 7, wherein indicating an adjustment to a target phase, setting a path adjustment parameter corresponding to the target phase to run before its corresponding phase is implemented, comprises: Under the condition that n maximum time sequence difference values M 1 ,M 2 ,…,M n corresponding to the time sequence difference variance which is not smaller than the preset time sequence consistency threshold value are time sequence difference variances between the T-X stage and the T stage, setting the maximum time sequence difference value M 1 ,M 2 ,…,M n to run before implementation of the T-X stage so as to optimize the time sequence consistency; If the maximum timing difference value M 1 ,M 2 ,…,M n is a negative number, adding Yan Di T-X phase n violating the timing constraint of the path group; If the maximum timing difference value M 1 ,M 2 ,…,M n is positive, the timing constraint of the n violating path group in the T-X stage is relaxed.
9. The method of claim 1, wherein entering a signature verification comprises: After the signing verification is finished, reading time sequence data from a time sequence database of the signing verification, and creating a violation path group corresponding to static time sequence analysis; Analyzing and calculating to obtain path adjustment parameters corresponding to the violation path group in the wiring stage and the verification stage and the time sequence difference condition of the violation path group in the two stages; According to the time sequence difference conditions in the two stages, indicating to the wiring stage to adjust or indicating to enter the next flow; If the next flow is instructed, the layout and the wiring are completed, signature verification is completed, and if the adjustment is instructed to the wiring stage, the path adjustment parameters corresponding to the violation path group in the wiring stage and the signature verification stage are set to run before the wiring stage is implemented, and the wiring stage is repeated to optimize the time sequence consistency.
10. The method of claim 1, wherein when the violating path is grouped by the module hierarchy name of each of the transmitting trigger and the capturing trigger in the violating path, the higher the number of the module hierarchy names, the more violating paths in each violating path group, the fewer the number of violating path groups can be created, and the lower the fine granularity of the optimized timing consistency; The lower the number of levels of the module hierarchy names, the fewer the time sequence violation paths contained in each violation path group, the more violation path groups can be created, and the higher the fine granularity of the optimized time sequence consistency.
11. The tool for optimizing the time sequence consistency is characterized by comprising a plurality of interfaces, a plurality of data processing units and a plurality of data processing units, wherein the interfaces are used for reading time sequence data from a time sequence database of each stage after the wiring stage of the first physical design is finished; the creating module is used for creating a violation path group corresponding to each stage based on the time sequence data; The analysis and calculation module is used for analyzing and calculating path adjustment parameters corresponding to each violation path group in different stages and time sequence difference conditions of each violation path group in different stages; The indication module is used for indicating adjustment to the target stage or indicating to enter the next flow according to the time sequence difference condition; And the execution module is used for entering verification of signing and displaying verification process if the next flow is indicated, and setting the path adjustment parameters corresponding to the target stage to run before the implementation of the target stage if the adjustment is indicated to the target stage.
12. The tool of claim 11, wherein the tool further comprises: a user interface for receiving user operations/selections, the operations/selections comprising: the first operation instruction is used for instructing the creation module to create a violation path group corresponding to each stage based on the time sequence data and displaying the violation path group corresponding to each stage through the user interface; The second operation instruction is used for indicating the analysis and calculation module to analyze and calculate the path adjustment parameters corresponding to the violation path groups in different stages and the time sequence difference conditions of the violation path groups in different stages, and displaying the path adjustment parameters and the time sequence difference conditions; The first selection instruction is used for selecting any two stages, indicating the analysis and calculation module to analyze and calculate the path adjustment parameters corresponding to each violation path group in the two stages and the time sequence difference condition of each violation path group in the two stages, and displaying the path adjustment parameters and the time sequence difference condition; The system comprises an instruction module, a target stage, a second selection instruction and a third operation instruction, wherein the instruction module is used for selecting the instruction module to execute target operation, the target operation comprises the instruction of adjusting a target stage or the instruction of entering a next flow, the third operation instruction is used for instructing the execution module to execute the target operation, if the target operation is the instruction of entering the next flow, the process of signing verification is entered and the signing verification is displayed, if the target operation is the instruction of adjusting the target stage, the path adjustment parameters corresponding to the target stage are set to run before the implementation of the target stage, and the data of the path adjustment parameters corresponding to the target stage are displayed.
13. A computer program product comprising computer programs/instructions which when executed by a processor implement the method of optimizing timing consistency of any of claims 1 to 10.

Description

Method, tool and program product for optimizing time sequence consistency Technical Field The present application relates to the field of chip design, and more particularly, to a method, tool and computer program product for optimizing timing consistency. Background With the physical design difficulty of the high-performance chip, especially the optimization convergence difficulty of the time sequence, the project iteration period is longer and longer, and thus, the time sequence accuracy, consistency and iteration speed of the physical design flow are required to be improved by a designer. However, the problem of timing difference exists in the current physical design process, which causes that the real critical path of the chip is hidden and ignored in the early stage of the design flow, and is actually exposed after wiring, so that the optimization of the critical path is not in place, and the convergence of the timing target is affected. At present, the time sequence consistency of the optimization flow is mainly realized through constraint such as clock period or time sequence uncertainty in the early stage of tightening, and judgment is usually carried out according to experience of a designer, so that the situation of over-tight constraint or over-loose constraint is easy to occur. When the time sequence constraint is too strict, too many units such as buffers are introduced, so that the area and winding resources are tensed, the problem of wiring congestion is aggravated, or more low threshold voltage units are introduced, and the power consumption of a chip is greatly increased. Too loose results in less than optimal critical paths and timing targets are difficult to achieve. Disclosure of Invention In view of the problems, the application provides a coupling construction method of a mine underground distributed optical fiber acoustic sensing system, which has the advantages of high construction efficiency, reliable coupling and excellent protection, so as to maximize the monitoring performance and service life of a DAS system and overcome the defects of the prior art. In a first aspect, an embodiment of the present application provides a method for optimizing timing consistency, including: After the wiring stage of the first physical design is finished, reading time sequence data from a time sequence database of each stage; creating a violation path group corresponding to each stage based on the time sequence data; Analyzing and calculating to obtain the corresponding path adjustment parameters of each violation path group in different stages and the time sequence difference condition of each violation path group in different stages. According to the time sequence difference condition, indicating to the target stage to adjust or indicating to enter the next flow; if the next flow is indicated, signature verification is entered, if the adjustment is indicated to the target stage, the path adjustment parameters corresponding to the target stage are set to run before the implementation of the target stage, so as to optimize the time sequence consistency. Optionally, creating a violation path group corresponding to each stage based on the time sequence data includes: after the wiring stage of the first physical design is finished, grouping the time sequence data of each stage according to a preset grouping strategy, and creating a corresponding violation path group for all time sequence violation paths in the time sequence data of each stage. Optionally, grouping the time sequence data of each stage according to a preset grouping policy, and creating a corresponding violation path group for all time sequence violation paths in the time sequence data of each stage, including: In each time sequence data, all time sequence violation paths are grouped according to the names of the transmitting trigger and the capturing trigger or the module level name, and a violation path group in the corresponding stage of the time sequence data is created. Optionally, the module hierarchy names comprise 1-N-level hierarchy names, and grouping all the time sequence violation paths according to the names of the transmitting trigger and the capturing trigger or the module hierarchy names comprises the following steps: Taking the name of a transmitting trigger in the time sequence violation path as a path group starting point of a packet, taking the name of a capturing trigger as a path group end point of the packet, and creating a violation path group, wherein the violation path group comprises a plurality of time sequence violation paths; Taking the module level name of any one of the timing violation paths as a path group starting point of a packet, and taking the module level name of the capturing trigger at the same level as the module level name of any one of the emission triggers as a path group end point of the packet, wherein the higher the level number of the module level names, the fewer the number of violation