CN-121981071-A - Wafer-level chip, board card and electronic equipment

Abstract

The application discloses a wafer-level chip, a board card and electronic equipment, wherein the wafer-level chip comprises a plurality of computing blocks which are arranged on a wafer in an array manner, each computing block comprises at least one computing node and storage units distributed on the periphery of the computing block, a wafer bus comprises at least one central switching node which is arranged in a central area of the wafer, a plurality of signal channels which extend from the edge of the wafer to the central switching node, each signal channel is used for connecting a corresponding IO interface and the central switching node, and a plurality of sub-switching nodes which are distributed on each signal channel and are connected with the computing nodes in the corresponding computing block. The application effectively ensures the consistency of the storage access bandwidth and the delay in the whole wafer range, and remarkably eliminates the problem of unbalanced load caused by the difference of physical distances.

Inventors

• OUYANG PENG
• LI XIUDONG

Assignees

• 北京清微智能科技股份有限公司

Dates

Publication Date

20260505

Application Date

20260402

Claims (10)

1. 1. A wafer level chip, comprising: the plurality of computing blocks are arranged on the wafer in an array manner, and each computing block comprises at least one computing node and storage units distributed around the computing block; The wafer bus comprises at least one central switching node arranged in a central area of the wafer, a plurality of signal channels extending from the edge of the wafer to the central switching node, a plurality of sub-switching nodes distributed on the signal channels and connected with the corresponding computing nodes in the computing blocks, wherein each signal channel is used for connecting the corresponding IO interface with the central switching node.
2. 2. The wafer level chip of claim 1, wherein when the wafer bus comprises a plurality of central switching nodes, the plurality of central switching nodes are interconnected by a two-dimensional network topology.
3. 3. The wafer level chip of claim 2, wherein the central switching nodes are interconnected by a Mesh network.
4. 4. The wafer level chip of claim 1, wherein the plurality of sub-switching nodes are respectively serially connected to each of the signal paths.
5. 5. The wafer level chip of claim 4, wherein each of the signal paths comprises: The first transmission path is connected with the central switching node and the corresponding IO interface; A second transmission path connecting the central switching node and the sub-switching nodes; And the third transmission path is connected with the sub-switching node and the corresponding IO interface.
6. 6. The wafer level chip of claim 4, wherein each of said sub-switching nodes comprises: a first port for connecting a computing node; A second port for connecting to a central switching node; and the third port is used for connecting the corresponding IO interface.
7. 7. The wafer level chip of claim 6, wherein the sub-switching node includes at least two first ports each connected to a compute node in an adjacent compute block.
8. 8. The wafer-level chip of claim 1, wherein at least one compute node of a compute block of a non-central area of the wafer is connected with a corresponding IO interface.
9. 9. A board comprising the wafer level chip of any one of claims 1-8.
10. 10. An electronic device comprising the board card of claim 9.

Description

Wafer-level chip, board card and electronic equipment Technical Field The application relates to the technical field of large model quantification, in particular to a wafer-level chip, a board card and electronic equipment. Background Wafer-SCALE ENGINE (WSE) is a leading-edge integrated circuit technology that aims to design, fabricate and package the entire Wafer (or a substantial portion thereof) as a single, large chip. Compared with the traditional mode of cutting a wafer into a plurality of independent chips and then assembling the chips through an external interconnection system, the wafer-level chip has the advantages that all functional units such as a computing core, a memory, a communication network and the like are integrated into a huge continuous structure, so that the on-chip communication bandwidth is remarkably improved, the communication delay is reduced, and the ultra-large-scale parallel computation is realized, thereby showing great potential in applications requiring extremely high bandwidth, extremely low delay such as AI computing power and the like. However, the existing wafer-level chip technology still faces many challenges and drawbacks, especially in terms of data access balance, in the conventional wafer-level chip design, the computing nodes on the wafer-level chip adopt a Mesh networking mode, and the IO interface is disposed at the edge of the wafer. This results in compute nodes at the edge of the wafer having higher bandwidth and lower latency when accessing external data, while compute nodes at the center of the wafer have lower bandwidth and higher latency when accessing external data due to their greater distance from the IO interface. This significant access latency difference can lead to load imbalance between different compute nodes, severely impacting the performance and efficiency of the overall wafer-level chip system. In summary, the existing wafer-level chip has significant drawbacks in achieving balance of storage access between computing nodes, optimizing data transmission efficiency, and interconnection topology while pursuing excellent performance. This section is intended to provide a background or context to the embodiments of the invention that are recited in the claims. The description herein is not admitted to be prior art by inclusion in this section. Disclosure of Invention In order to solve at least one of the above problems in the prior art, an embodiment of the present application provides a wafer level chip, a board card and an electronic device. According to a first aspect of the present application, there is provided a wafer level chip comprising: the plurality of computing blocks are arranged on the wafer in an array manner, and each computing block comprises at least one computing node and storage units distributed around the computing block; The wafer bus comprises at least one central switching node arranged in a central area of the wafer, a plurality of signal channels extending from the edge of the wafer to the central switching node, a plurality of sub-switching nodes distributed on the signal channels and connected with the corresponding computing nodes in the computing blocks, wherein each signal channel is used for connecting the corresponding IO interface with the central switching node. In some embodiments of the present application, when the wafer bus includes a plurality of central switching nodes, the plurality of central switching nodes are interconnected by a two-dimensional network topology. In some embodiments of the present application, the central switching nodes are interconnected by using a Mesh network. In some embodiments of the present application, the plurality of sub-switching nodes are respectively connected in series to each of the signal paths. In some embodiments of the application, each of the signal paths includes: The first transmission path is connected with the central switching node and the corresponding IO interface; A second transmission path connecting the central switching node and the sub-switching nodes; And the third transmission path is connected with the sub-switching node and the corresponding IO interface. In some embodiments of the present application, each of the above sub-switching nodes includes: a first port for connecting a computing node; A second port for connecting to a central switching node; and the third port is used for connecting the corresponding IO interface. In some embodiments of the present application, the sub-switching node includes at least two first ports respectively connected to the computing nodes in the adjacent computing blocks. In some embodiments of the present application, at least one computing node of the computing block of the non-central area of the wafer is connected to a corresponding IO interface. According to a third aspect of the present application there is also provided a board card comprising a wafer level chip as described above. According to a fourth as