CN-121981183-A - Parallel polynomial gradient computing system and method based on CMOS (complementary metal oxide semiconductor) nerve synapse transistor

CN121981183ACN 121981183 ACN121981183 ACN 121981183ACN-121981183-A

Abstract

The invention discloses a parallel polynomial gradient computing system and a method based on a CMOS (complementary metal oxide semiconductor) nerve synaptic transistor, and relates to the technical field of computing systems. The parallel polynomial gradient computing system based on the CMOS nerve synapse transistor adopts a basic computing unit comprising at least one CMOS transistor, configures the CMOS transistor to show the dual mode characteristics of neuron behavior and synapse behavior under a floating substrate operation mode, combines a parallel array architecture, realizes nerve morphology computing hardware based on a standard CMOS process, utilizes a mature CMOS manufacturing technology, avoids special materials and post-integration processes required by emerging devices such as memristors and the like, improves the manufacturability and yield of the system, reduces the production cost, and simultaneously effectively overcomes the problems of large difference among devices and state drift existing in a memristor scheme due to the inherent device consistency and long-term stability of the CMOS transistor, and realizes high-precision polynomial gradient computing.

Inventors

ZHAO CHUN
WU RUI

Assignees

深圳市华芯邦科技有限公司

Dates

Publication Date: 20260505
Application Date: 20260403

Claims (10)

1. A parallel polynomial gradient computing system based on CMOS neural synaptic transistors, comprising: A plurality of basic computational units, each basic computational unit comprising at least one CMOS transistor configured to exhibit dual mode characteristics of neuronal behavior and synaptic behavior in a floating substrate mode of operation; A voltage pulse programming circuit connected to each of the basic computing units for applying a voltage pulse to the CMOS transistor to adjust its conductive state, thereby programming the basic computing units to simulate synaptic weights; And a parallel array architecture, which organizes the plurality of basic computing units into an array for parallel execution of polynomial gradient computation.
2. The CMOS neurite transistor based parallel polynomial gradient computing system according to claim 1, wherein the floating substrate operation mode is to float the substrate terminal of the CMOS transistor and control the threshold behavior thereof by adjusting the gate voltage and the substrate bias so as to realize the firing and recovery process of the neuron.
3. The CMOS neurite transistor based parallel polynomial gradient computing system according to claim 2, wherein the CMOS transistor achieves the enhancement and suppression of the synaptic weight and supports short-term and long-term plasticity by applying voltage pulses of different magnitudes, widths or frequencies in a floating substrate operation mode.
4. The CMOS neural synaptic transistor-based parallel polynomial gradient computing system of claim 1, wherein each basic computational cell is a 2-transistor cell comprising a first CMOS transistor configured as an analog neuron and a second CMOS transistor configured as an analog synapse, and the substrates of both the first CMOS transistor and the second CMOS transistor are floating.
5. The parallel polynomial gradient computing system based on CMOS neural synaptic transistors as claimed in claim 4, wherein the first CMOS transistor has its gate connected to an input signal line, its drain and source connected to power and ground, respectively, and the neuron threshold adjustability is achieved by a substrate resistance adjustment circuit, and the second CMOS transistor has its gate connected to a pulse programming line, its drain and source connected to input and output lines, respectively, and its channel conductance changed by a gate voltage pulse to store synaptic weights.
6. The CMOS neurite transistor based parallel polynomial gradient computing system according to claim 1, wherein the parallel array architecture is a cross array structure in which each basic computing unit is located at the crossing point of a word line for an input signal or a control signal and a bit line for an output signal so that a plurality of units can perform multiply-accumulate operation at the same time.
7. The CMOS neurite transistor based parallel polynomial gradient computing system according to claim 6, further comprising a row driver for supplying a voltage pulse sequence to the word line and a column readout circuit for collecting bit line current or voltage and converting into digital signals to complete gradient computation.
8. The CMOS-neural-synaptic-transistor-based parallel polynomial gradient computing system of claim 7, further comprising a control logic unit that generates the update weights required for the gradient descent algorithm according to a predetermined polynomial function and controls the row driver to generate corresponding voltage pulses to program the synaptic weights of the respective basic computing units.
9. The CMOS-neurosynaptic-transistor based parallel polynomial gradient computing system of claim 8, wherein the control logic unit is further configured to read the array output in each iteration, calculate a polynomial gradient value, and adjust the voltage pulse parameters based on the gradient value to update the weights until convergence.
10. A parallel polynomial gradient calculating method based on a CMOS neurite transistor, which is applied to a parallel polynomial gradient calculating system based on a CMOS neurite transistor according to any one of claims 1 to 9, and is characterized by comprising the following steps: step S1, configuring a plurality of basic computing units into CMOS transistors working in a floating substrate operation mode and organizing the CMOS transistors into a parallel array; step S2, applying an initialization voltage pulse to each basic calculation unit through a voltage pulse programming circuit so as to set initial synaptic weights; step S3, the variable value of the polynomial is used as an input signal to be applied to a row line of the array, and the output of each unit is calculated in parallel through the array, so that the polynomial value and the intermediate result related to the gradient thereof are obtained; S4, reading column output of the array, converting the column output into a digital signal through a reading circuit, and calculating a gradient according to a preset gradient descent algorithm; Step S5, generating update pulses by the control logic unit according to the calculated gradient, and adjusting the synaptic weights of the corresponding basic calculation units by the voltage pulse programming circuit; and S6, repeating the steps S3 to S5 until the polynomial gradient meets the convergence condition or reaches the preset iteration times.

Description

Parallel polynomial gradient computing system and method based on CMOS (complementary metal oxide semiconductor) nerve synapse transistor Technical Field The invention relates to the technical field of computing systems, in particular to a parallel polynomial gradient computing system and method based on a CMOS (complementary metal oxide semiconductor) neurosynaptic transistor. Background In the prior art, in order to realize efficient polynomial gradient calculation to accelerate an optimization algorithm, researchers propose various hardware acceleration schemes, for example NorthPole chips issued by IBM corporation realize large-scale matrix operation on a chip through an integrated storage and calculation unit, improve the efficiency of neural network reasoning, and in addition, a cross array structure based on memristors is widely studied for simulating vector-matrix multiplication by storing weights in the conductance of memristors, so as to support hardware acceleration of the optimization algorithm such as gradient descent and the like, and the schemes exhibit excellent energy efficiency and calculation throughput under specific application scenes. However, the above-mentioned prior art still has the following problems in practical application, for the cross array scheme based on memristors, although memristors have non-volatility, programmability and high density integration potential, the memristors usually adopt special materials such as metal oxide, the manufacturing process is incompatible with the standard CMOS process, additional integration is required in the subsequent process of chip manufacturing, which increases the manufacturing cost and complexity, moreover, the yield of the memristors is generally lower, it is difficult to ensure that all units can normally work in a large-scale array, and the conductivity characteristics among the devices have differences, so that the calculation precision is reduced and the algorithm is difficult to converge, state drift easily occurs under continuous operation, the resistance value of the memristors changes with time or pulse times, the long-term stability of weight is affected, and meanwhile, the leakage current problem in the cross array further aggravates the power consumption and signal interference, the expansion of the array scale is limited, and for the digital acceleration chip such as NorthPole, although the CMOS process is adopted, the calculation unit is still based on the traditional digital logic, the parallelism and the energy efficiency advantage are difficult to fully utilize, and the parallelism of analog calculation are difficult, and the realization of the digital circuit resources are still required to be realized when the high-order multi-stage calculation gradient is realized, and the parallelism and the complexity and the CMOS technology are still required to be realized, and the hardware is mature. Disclosure of Invention Aiming at the defects of the prior art, the invention provides a parallel polynomial gradient computing system and a parallel polynomial gradient computing method based on a CMOS (complementary metal oxide semiconductor) nerve synapse transistor, which are characterized in that a basic computing unit comprising at least one CMOS transistor is adopted, the CMOS transistor is configured to show the dual mode characteristics of neuron behavior and synapse behavior under a floating substrate operation mode, and simultaneously, the parallel array architecture is combined. The invention is realized by the following technical scheme that the parallel polynomial gradient computing system based on the CMOS nerve synaptic transistor comprises: A plurality of basic computational units, each basic computational unit comprising at least one CMOS transistor configured to exhibit dual mode characteristics of neuronal behavior and synaptic behavior in a floating substrate mode of operation; A voltage pulse programming circuit connected to each of the basic computing units for applying a voltage pulse to the CMOS transistor to adjust its conductive state, thereby programming the basic computing units to simulate synaptic weights; And a parallel array architecture, which organizes the plurality of basic computing units into an array for parallel execution of polynomial gradient computation. Preferably, the floating substrate operation mode refers to floating the substrate terminal of the CMOS transistor and controlling the threshold behavior thereof by adjusting the gate voltage and the substrate bias to achieve the firing and recovery process of the neuron. Preferably, the CMOS transistor achieves enhancement and suppression of synaptic weights and supports short-term and long-term plasticity by applying voltage pulses of different magnitudes, widths or frequencies in a floating substrate mode of operation. Preferably, each basic computational cell is a 2-transistor cell comprising a first CMOS transistor configured as an a