CN-121981289-A - Quantum mode inverse operator, quantum chip and quantum computer

CN121981289ACN 121981289 ACN121981289 ACN 121981289ACN-121981289-A

Abstract

The embodiment of the application discloses a quantum mode inverse operator, a quantum chip and a quantum computer, wherein the quantum mode inverse operator comprises a register U, v, s, r, f and a quantum logic gate U 1 、U 2 、U 3 , the quantum logic gate U 1 is used for realizing four selection branches in a Kaliski algorithm according to U, v, s, r, the quantum logic gate U 2 is used for realizing |a ‑1 modq > according to |a ‑1 2 l modq when the quantum state |u > of U is not |1> and the quantum state |v > of v is not |0>, and the quantum logic gate U 1 is controlled by f to realize the iterative updating of |u >, |v >, |s >, so that |s > is |1> and |v > is |0>, and the quantum logic gate U 3 is used for realizing |a ‑1 modq > according to |a ‑1 2 l modq >. By adopting the embodiment of the application, the quantum mode inverse operation can be realized, the basic operation circuit of the quantum computer can be improved, and the blank in the aspect is filled.

Inventors

LI YE
Request for anonymity

Assignees

本源量子计算科技（合肥）股份有限公司

Dates

Publication Date: 20260505
Application Date: 20241028

Claims (10)

1. A quantum-mode inverse operator, wherein the quantum-mode inverse operator comprises a register U, v, s, r, f and a quantum logic gate U 1 、U 2 、U 3 ; The quantum logic gate U 1 is configured to implement four selection branches in the Kaliski algorithm according to the U, v, s, r; The quantum logic gate U 2 is configured to, when the quantum state |u > of the U is not |1> and the quantum state |v > of the v is not |0>, control the quantum logic gate U 1 to update the number of operations of the Kaliski algorithm by the f acting thereon, so that the initial states of the |u > and the |v > are |q > and the |r > are |a - 1 2 l modq >, respectively, wherein the |q > is a quantum state corresponding to a modulus q, the |a -1 2 l modq is a quantum state corresponding to-a -1 2 l modq, the a is an input number, and the l is the number of operations of the Kaliski algorithm, and the |u >, |v >, |s >, |r >, |f are respectively |q >, |1> |0> |1> |0 >. The quantum logic gate U 3 is used for realizing the |a -1 modq > according to the |a -1 2 l modq >.
2. The quantum-mode inverse operator of claim 1, wherein said four selection branches are respectively: if the u is even, assigning u/2 to the u and 2s to the s; If the u is odd and the v is even, assigning v/2 to the v and 2r to the r; If both the u and the v are odd and the u is greater than the v, (u-v)/2 is assigned to the u, r+s is assigned to the r, and 2s is assigned to the s; if both the u and the v are odd and the u is less than or equal to the v, (v-u)/2 is assigned to the v, r+s is assigned to the s, and 2r is assigned to the r.
3. The quantum mode inverse operator of claim 2, wherein the quantum logic gate U 1 comprises a quantum logic gate U 4 and a quantum logic gate U 5 ; The quantum logic gate U 4 is configured to implement four selection conditions of the four selection branches, where the four selection conditions include that U is even, U is odd, v is even, U and v are both odd, U is greater than v, U and v are both odd, and U is less than or equal to v; The quantum logic gate U 5 is configured to implement four execution branches of the four selection branches, where the four execution branches include assigning U/2 to the U and 2s to the s, v/2 to the v and 2r to the r, (U-v)/2 to the U, r+s to the r, and 2s to the s, (v-U)/2 to the v, r+s to the s, and 2r to the r.
4. The quantum-mode inverse operator according to claim 3, further comprising registers compare, aux1, aux2, and mi in initial state |0 >; The quantum logic gate U 4 includes an not gate that is sequentially subject to the U virtual control on the aux2, an not gate that is subject to the v and the aux2 virtual control on the mi, a subtractor that is subject to the U, the v, and the compare, an not gate that is subject to the aux2 virtual control on the aux1, an not gate that is subject to the aux1 virtual control on the aux2 and the mi, an not gate that is subject to the mi virtual control on the aux1, an not gate that is subject to the aux2 virtual control on the aux1, an adder that is subject to the U, the v, and the compare; The output state |10> of the aux2 and mi is used to represent that the u is even, the output state |01> of the aux2 and mi is used to represent that the u is odd and the v is even, the output state |11> of the aux2 and mi is used to represent that the u and the v are both odd and the u is greater than the v, and the output state |00> of the aux2 and mi is used to represent that the u and the v are both odd and the u is less than or equal to the v.
5. The quantum-mode inverse operator according to claim 3, further comprising registers compare, aux2, and mi in initial state |0 >; The quantum logic gate U 4 includes an not gate that is sequentially subjected to the U virtual control to the aux2, an not gate that is subjected to the v and the aux2 virtual control to the mi, a subtractor that is subjected to the U, the v, and the compare, an not gate that is subjected to the mix real control to the aux2 virtual control to the not gate, an not gate that is subjected to the mix real control to the aux2, and an adder that is subjected to the U, the v, and the compare; The output state |10> of the aux2 and mi is used to represent that the u is even, the output state |01> of the aux2 and mi is used to represent that the u is odd and the v is even, the output state |11> of the aux2 and mi is used to represent that the u and the v are both odd and the u is greater than the v, and the output state |00> of the aux2 and mi is used to represent that the u and the v are both odd and the u is less than or equal to the v.
6. A quantum modular inverse operator as claimed in claim 3, wherein the quantum logic gate U 5 comprises a modulo-double divider acting on the U and a modulo-double multiplier acting on the s, which are in turn virtually controlled by the aux2, a modulo-double divider acting on the v and a modulo-double multiplier acting on the r, which are virtually controlled by the aux2, a subtractor acting on the U and the v and an adder acting on the s and the r, which are virtually controlled by the aux2 and the mi, a modulo-double divider acting on the U and a modulo-double multiplier acting on the s, which are virtually controlled by the aux2 and the mi, a subtractor acting on the U and the v and an adder acting on the s and the r, which are virtually controlled by the aux2 and the mi, a modulo-double divider acting on the v and a modulo-double multiplier acting on the r, which are virtually controlled by the aux2 and the mi, and a modulo-double multiplier acting on the r, which are virtually controlled by the aux2 and the aux 2; and u, v, s, r is used for storing the |u >, |v >, |s >, and|r >, which are updated in each iteration respectively.
7. The quantum-mode inverse operator according to claim 3, further comprising a register k having an initial state of |0 >; The quantum logic gate U 2 comprises NOT gates which are sequentially subjected to k real control on the f, v virtual control on the f, f and f virtual control on the k, and INC gates for realizing addition operation of the numerical value represented by the quantum state.
8. The quantum modular inverse operator of any of claims 1-7 wherein the quantum logic gate U 3 comprises l modulo-double dividers for performing l modulo-double division operations on the |a -1 2 l modq > to yield |a -1 modq and a modulo-negative algorithm for subtracting the |q > from the |a -1 modq > to yield |a -1 modq >.
9. A quantum chip comprising a quantum modular inverse operator according to any one of claims 1-7.
10. A quantum computer comprising the quantum chip of claim 8.

Description

Quantum mode inverse operator, quantum chip and quantum computer Technical Field The invention relates to the technical field of quantum computing, in particular to a quantum mode inverse operator, a quantum chip and a quantum computer. Background A processor is one of the core components of a computer system, which is responsible for executing various instructions and processing data. The basic arithmetic circuitry is then the basic unit constituting the processor, which cooperate to carry out complex computational tasks. The modulus operation (Modular Arithmetic) is one of the basic operations, and the core idea is to limit the numerical value to a fixed range, and realize the cycle and periodicity through the modulus operation, so that the modulus operation is widely applied to the fields of cryptography, computer science, quantum computation and the like. Among the modular operations, the modular inverse operation is the most complex, time-consuming operation among finite field operations, and the most difficult to implement by hardware. At present, the research on the modular inversion algorithm at home and abroad is quite plentiful, and a plurality of modular inversion algorithms suitable for a prime number domain and a binary domain are provided. Among the more well-known algorithms are the Fermat algorithm based on the Fermat theorem (Fermat theshem), the extended Euclidean algorithm, and the Montgomery modulo inversion algorithm. Since the number of times of using the modulo multiplication is too large when using the small rule of the Fermat to find the modulo inversion in the prime number domain and the binary domain, it is very unrealistic to design the modulo inversion hardware on the double finite domain by using the fee Ma Suanfa. Most of the hardware designs of modulo inversion operation are currently implemented based on extended Euclidean algorithms. However, the algorithm is only oriented to the binary domain, the expansion from the binary domain to the prime number domain cannot be realized, the area complexity is very high, and the hardware resource consumption is large. Quantum computers are still in the early stages of development, and despite some significant breakthroughs, they still present many challenges and places to be perfected in terms of the fundamental arithmetic circuitry of modulus. How to design a quantum operator that can perform modulo inversion operation is one of the main challenges at present. Disclosure of Invention The embodiment of the application provides a quantum mode inverse operator, a quantum chip and a quantum computer, which can realize quantum mode inverse operation, are favorable for perfecting a basic operation circuit of the quantum computer and fill the gap in the aspect. The first aspect of the embodiment of the application provides a quantum mode inverse operator, which comprises a register U, v, s, r, f and a quantum logic gate U 1、U2、U3; The quantum logic gate U 1 is configured to implement four selection branches in the Kaliski algorithm according to the U, v, s, r; The quantum logic gate U 2 is configured to, when the quantum state |u > of the U is not |1> and the quantum state |v > of the v is not |0>, control the quantum logic gate U 1 to update the quantum states |u >, |v >, s, r of the r in an iterative manner through the f, so that the |u > is |1> and the |v > is |0>, the |s > is |q > and the |r > is |a -12l modq >, wherein the |q > is a quantum state corresponding to the modulus q, the |a -12l modq > is a quantum state corresponding to the-a -12l modq, the a is an input number, the l is the number of operations of the Kaliski algorithm, and the initial states of the |u >, |v >, |s >, |f > are q >, |1> |0> |1>, respectively. The quantum logic gate U 3 is used for realizing the |a -1 modq > according to the |a -12l modq >. In some examples, the four selection branches are respectively: if the u is even, assigning u/2 to the u and 2s to the s; If the u is odd and the v is even, assigning v/2 to the v and 2r to the r; If both the u and the v are odd and the u is greater than the v, (u-v)/2 is assigned to the u, r+s is assigned to the r, and 2s is assigned to the s; if both the u and the v are odd and the u is less than or equal to the v, (v-u)/2 is assigned to the v, r+s is assigned to the s, and 2r is assigned to the r. In some examples, the quantum logic gate U 1 includes a quantum logic gate U 4 and a quantum logic gate U 5; The quantum logic gate U 4 is configured to implement four selection conditions of the four selection branches, where the four selection conditions include that U is even, U is odd, v is even, U and v are both odd, U is greater than v, U and v are both odd, and U is less than or equal to v; The quantum logic gate U 5 is configured to implement four execution branches of the four selection branches, where the four execution branches include assigning U/2 to the U and 2s to the s, v/2 to the v and 2r to the r, (U-v)/2 to