CN-121981958-A - PCB defect detection method based on improved YOLO11s

CN121981958ACN 121981958 ACN121981958 ACN 121981958ACN-121981958-A

Abstract

The invention belongs to the field of computer vision and circuit board defect detection, and discloses a PCB defect detection method based on improved YOLO11 s. The method comprises the following steps of S1, establishing a PCB defect detection data set, expanding the data set for defects in the data set, dividing the expanded data set according to a training set, namely a verification set, namely a test set=7:2:1, S2, establishing a PCB defect detection network based on improved YOLO11S, S3, training the PCB defect detection network, namely adjusting and configuring corresponding parameters to train the PCB defect detection network to obtain a PCB defect detection model, S4, storing a trained optimal weight file into the network model of the improved YOLO11S, and then inputting a PCB image to be detected into the defect detection model based on the trained weight file, identifying a defect target of the PCB image, and obtaining position, confidence and category information of the defects.

Inventors

Ma Pengsen
ZHANG FENGTAO
HAO WEI
LIN XINGWEI
WANG LEI
SHI SHENGZHI
GAO KEJIN

Assignees

西安益翔航电科技有限公司

Dates

Publication Date: 20260505
Application Date: 20251227

Claims (10)

1. The PCB defect detection method based on the improved YOLO11s is characterized by comprising the following steps of: S1, establishing a PCB defect detection data set, expanding the data set for defects in the data set, and dividing the expanded data set according to a training set, namely a verification set, namely a test set=7:2:1; s2, establishing a PCB defect detection network based on improved YOLO 11S; S3, training a PCB defect detection network, namely adjusting and configuring corresponding parameters to train the PCB defect detection network to obtain a PCB defect detection model; And S4, saving the trained optimal weight file to a network model of the improved YOLO11S, inputting the PCB image to be detected into a defect detection model based on the trained weight file, identifying a defect target of the PCB image, and obtaining the position, the confidence coefficient and the category information of the defect.
2. The YOLO 11S-based PCB defect detection method of claim 1, wherein the defect types in the dataset of step S1 include holes, mouse bites, opens, shorts, strays, and copper clutter; the expansion mode comprises geometric transformation, color disturbance and mosaic data enhancement.
3. The method for detecting PCB defects based on YOLO11S as recited in claim 2, wherein the PCB defect detection network comprises a Backbone feature extraction network Backbone, a neck Neck, and a task header Head in step S2.
4. The YOLO11 s-based PCB defect detection method of claim 3, wherein the backbone feature extraction network extracts multi-scale semantic features from the input image, comprising DWConv modules, C3K2 modules, AIFI modules, and C2PSA modules, for a total of 11 layers; Layer 1 places 1 DWConv modules for initial downsampling to extract shallow texture features P1, the output of which is connected to layer 2; layer 2 places 1 DWConv module for 2 nd downsampling to enhance edge and contour information features, outputs feature P2 and connects to layer 3; the 3 rd layer is provided with 2C 3K2 modules for lightening the residual error module, so that local and global features are fused, and the output of the residual error module is connected to the 4 th layer; the method comprises the steps of arranging a DWConv th module on a layer 4, carrying out 3 rd downsampling so as to enter a middle semantic space, outputting a characteristic P3 and connecting the characteristic P3 to the layer 5, arranging 2C 3K2 modules on the layer 5 for enhancing middle characteristics, improving target perception capability, enabling the output of the C3K2 modules to be connected to the layer 6, arranging 1 DWConv modules on the layer 6, carrying out 4 th downsampling so as to enter a deep semantic space, outputting the characteristic P4 and connecting the C4 to the layer 7, arranging 2C 3K2 modules on the layer 7, carrying out deep residual fusion, enhancing semantic expression, enabling the output of the C3K2 modules to be connected to the layer 8, arranging 1 DWConv modules on the layer 8, carrying out 5 downsampling, constructing high-semantic low-resolution characteristics P5 and connecting the C3K2 modules to the layer 9, enabling the C3K2 modules to be used for enhancing high-semantic characteristics, enabling the C3K2 modules to be adaptively connected to the layer 10, arranging 1 AIFI module on the layer 10, carrying out self-adaption fusion on the multi-layer characteristics, improving equilibrium information, enabling the C2 modules to be connected to the layer 11, arranging the C2 modules on the layer 11, carrying out the PSA 2 channels to be sequentially, and enabling the size of each channel to be increased by a network to be equal to the size of a channel, and each channel of the channel is reduced by the key 3, and each channel is sequentially and the channel is enlarged, and each size of the channel is enlarged by the size of a channel is reduced.
5. The YOLO11 s-based PCB defect detection method of claim 4, wherein SegNext attention mechanism is embedded in the output characteristics of Neck networks, and SegNext attention mechanism consists of encoder and decoder, expressed mathematically as follows: Wherein the input features are The output feature is Out, att represents the attention weight.
6. The YOLO11 s-based PCB defect detection method of claim 4, wherein Neck network is used to construct a multi-scale feature pyramid comprising 6 layers; Layer 1 is Upsample, upsampling the features of the P5 scale to the features of the P4 scale, whose output is connected to layer 2 of the Neck network, layer 2 is Concat, the upsampled features of the previous layer and the output features of layer 7 in the backbone network are spliced, whose output is connected to layer 3 of the Neck network, layer 3 is 2C 3K2 modules for compressing the fusion features to adapt the prediction of the mesoscale object, whose output is connected to layer 4 of the Neck network, layer 4 is Upsample, upsampling the output features of the previous layer, whose output is connected from P4 to P3, whose output is connected to layer 5 of the Neck network, layer 5 is Concat, the upsampled features of the previous layer and the output features of layer 5 in the backbone network are spliced, whose output is connected to layer 6 of the Neck network, layer 6 is 2C 3K2 modules, and continuing to compress the fusion features to adapt the prediction of the small scale object, whose output is connected to the Head network.
7. The YOLO11 s-based PCB defect detection method of claim 6, wherein the Head network is used for target prediction, comprising 10 layers; Layer 1 is 2 SegNext modules for decoding and attention enhancement of small objects, the output of which is connected to layer 2 of the Head network; layer 2 is Conv layer, which converts the P3 scale feature into P4 scale feature by downsampling and connects to layer 3 of the Head network; the method comprises the steps of layer 3, layer Concat, splicing the output characteristics of the upper layer with the layer 3 output characteristics of a Neck network, wherein the output of the layer 4 is connected to the layer 4 of a Head network, layer 4 is 2C 3K2 modules, the output of the layer 4 is connected to the layer 5 of the Head network, the layer 5 is 2 SegNext modules, the output of the layer 5 is connected to the layer 6 of the Head network, the layer 6 is Conv, the P4 scale characteristics are converted into the P5 scale characteristics through downsampling, the output of the layer 7 is Concat, the output characteristics of the upper layer are spliced with the 11 th output characteristics of a backbone network, the output of the layer 7 is connected to the layer 8 of the Head network, the layer 8 is 2C 3K2 modules, the output of the layer 5 is connected to the layer 9 of the Head network, the layer 9 is 2 SegNext modules, the decoding of the large target is connected to the layer 6 of the Head network, the output of the layer 10 is used for enhancing the confidence level of the target, the layer 10, and the output of the layer 10 is used for detecting the target class.
8. The YOLO11 s-based PCB defect detection method of claim 7, wherein the boundary box regression task is optimized using SIOU loss functions, the mathematical expression of which is: SIOU is to perform regression and optimization on the prediction frames and the real frames of three scales P3, P4 and P5 during layer 10 training of the Head network, and the specific flow comprises input image-output prediction frame-matching real frame-calculation SIOU loss-back propagation-iterative update.
9. An electronic device is characterized by comprising at least one processor and a memory connected with the processor, wherein the memory stores a computer program; The at least one processor executing the computer program stored by the memory causes the at least one processor to perform the improved YOLO11s based PCB defect detection method as claimed in any one of claims 1 to 8.
10. A computer readable storage medium, characterized in that the computer readable storage medium has stored therein a computer program executable by a processor to implement the improved YOLO11s based PCB defect detection method according to any of claims 1 to 8.

Description

PCB defect detection method based on improved YOLO11s Technical Field The invention belongs to the field of computer vision and circuit board defect detection, and particularly relates to a PCB defect detection method based on improved YOLO11 s. Background The PCB is a core component of an electronic device, and defect detection thereof is critical to product quality. The traditional detection method relies on manual visual inspection or traditional image processing technology, and has the problems of low efficiency and high omission rate. The YOLO series algorithm based on deep learning is excellent in target detection, but still faces the following problems in PCB defect detection: 1. the calculation complexity is high, the parameter quantity of the original convolution layer is large, and the original convolution layer is difficult to be deployed in edge equipment; 2. The small defect missing detection is that the feature fusion capability of the SPPF module is insufficient, so that the detection of fine defects (such as short circuit and open circuit) is difficult; 3. the characteristic expression capability is weak, and Neck part lacks dynamic focusing on key characteristics; 4. insufficient positioning accuracy-CIOU loss function has limitations on optimization of bounding box regression. The existing improvement scheme does not conduct targeted optimization aiming at the defect characteristics of the PCB, so that the detection accuracy is still insufficient, and practical application cannot be conducted well. Therefore, there is a need for an efficient, lightweight, and high-precision method for detecting defects in PCBs. Disclosure of Invention The invention aims to provide a PCB defect detection method and a storage medium based on improved YOLO11s, which solve the problems of low defect detection precision, high calculation resource consumption and the like of the existing PCB defect detection method by combining and optimizing a main network, multi-scale dynamic feature fusion, and coding and decoding structure attention enhancement and a loss function of the lightweight YOLO11s, and realize the following aims: (1) The mAP50=92.6% on the PKU-mark-PCB data set, which is improved by more than 10% compared with the original network; (2) The model size is less than or equal to 10MB, the model parameter is less than or equal to 5M, the image reasoning speed is more than or equal to 200FPS, and the calculation cost is reduced; (3) The method is enhanced, supports the detection of 6 types of defects (leak holes, rat bites, open circuits, short circuits, strays and copper impurities) and adapts to complex illumination and background interference. Technical proposal A PCB defect detection method based on improved YOLO11s comprises the following steps: S1, establishing a PCB defect detection data set, expanding the data set for defects in the data set, and dividing the expanded data set according to a training set, namely a verification set, namely a test set=7:2:1; s2, establishing a PCB defect detection network based on improved YOLO 11S; S3, training a PCB defect detection network, namely adjusting and configuring corresponding parameters to train the PCB defect detection network to obtain a PCB defect detection model; S4, saving the trained optimal weight file to a network model of improved YOLO11S, inputting the PCB image to be detected into a defect detection model based on the trained weight file, identifying a defect target of the PCB image, and obtaining the position, the confidence coefficient and the category information of the defect; further, the defect types in the dataset in step S1 include weep holes, mouse bites, opens, shorts, strays, and copper clutter; the expansion mode comprises geometric transformation, color disturbance and mosaic data enhancement. Further, in step S2, the PCB defect detection network includes a Backbone feature extraction network Backbone, a neck Neck, and a task header Head. Further, the backbone feature extraction network extracts multi-scale semantic features from the input image, including DWConv modules, C3K2 modules, AIFI modules, and C2PSA modules, for a total of 11 layers; Layer 1 places 1 DWConv modules for initial downsampling to extract shallow texture features P1, the output of which is connected to layer 2; layer 2 places 1 DWConv module for 2 nd downsampling to enhance edge and contour information features, outputs feature P2 and connects to layer 3; the 3 rd layer is provided with 2C 3K2 modules for lightening the residual error module, so that local and global features are fused, and the output of the residual error module is connected to the 4 th layer; the method comprises the steps of arranging a DWConv th module on a layer 4, carrying out 3 rd downsampling so as to enter a middle semantic space, outputting a characteristic P3 and connecting the characteristic P3 to the layer 5, arranging 2C 3K2 modules on the layer 5 for enhancing middle charact