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CN-121982984-A - Gate driving circuit

CN121982984ACN 121982984 ACN121982984 ACN 121982984ACN-121982984-A

Abstract

The application belongs to the technical field of display driving, and particularly relates to a gate driving circuit, which comprises N cascaded gate driving modules, wherein the nth-stage gate driving module comprises a pre-charging unit, a stage transmission output unit, a local brushing control unit and a driving output unit, wherein the pre-charging unit is configured to pre-charge a pre-charging control node, the stage transmission output unit is configured to output a current stage of stage transmission signal, the local brushing control unit is configured to control the pre-charging control node to be conducted with the driving control node if the current stage is a refreshing row in a local refreshing mode, the pre-charging control node is controlled to be disconnected with the driving control node if the current stage is a non-refreshing row, and the driving output unit is configured to output a current-stage gate driving signal.

Inventors

  • LAN TIAN
  • XU PEI

Assignees

  • 惠科股份有限公司

Dates

Publication Date
20260505
Application Date
20260408

Claims (10)

  1. 1. A gate driving circuit comprising N cascaded gate driving modules, wherein an nth stage gate driving module comprises: The precharge unit is connected with the precharge control node of the current stage and is configured to precharge the precharge control node through the level transmission signal of the n-j-th stage grid driving module; The stage transmission output unit is connected with the pre-charge control node and is configured to output a stage transmission signal of the current stage under the control of the voltage on the pre-charge control node; the local brush control unit is connected with the pre-charge control node and the driving control node of the current stage and is configured to control the pre-charge control node to be conducted with the driving control node if the current stage is a refresh row in a local refresh mode; and the driving output unit is connected with the driving control node and is configured to output a gate driving signal of the current stage under the control of the voltage on the driving control node.
  2. 2. The gate driving circuit according to claim 1, wherein the partial brush control unit includes: A state response subunit, connected to a state node of the current stage and at least one control signal terminal, configured to respond to the level state of the at least one control signal terminal, and form a potential corresponding to a refresh state of the current stage on the state node; An enable control subunit, connected to the state node and an enable node of a current stage, configured to output a corresponding driving enable signal to the enable node according to a potential on the state node; And the gating switch subunit is connected with the enabling node, the pre-charging control node and the driving control node and is configured to be controlled by a driving enabling signal on the enabling node so as to switch on or off the electric connection between the pre-charging control node and the driving control node.
  3. 3. The gate drive circuit of claim 2, wherein the state response subunit comprises: The control end of the first transistor is connected with a first control signal end, the first end of the first transistor is connected with the state node, and the second end of the first transistor is connected with a low level end; the control end of the second transistor is connected with the second control signal end, and the first end of the second transistor is connected with the level transmission output end of the n-j level grid driving module; And the first end of the first capacitor is connected with the second end of the second transistor, and the second end of the first capacitor is connected with the first end of the first transistor.
  4. 4. A gate drive circuit as recited in claim 3, wherein the enable control subunit comprises: And a third transistor, a control terminal of the third transistor is connected to the state node, a first terminal of the third transistor is connected to the second control signal terminal, and a second terminal of the third transistor is connected to the enable node.
  5. 5. The gate drive circuit of claim 2, wherein the state response subunit comprises: The control end of the first transistor is connected with a first control signal end, the first end of the first transistor is connected with the state node, and the second end of the first transistor is connected with a low level end; the control end of the second transistor is connected with the second control signal end, and the first end of the second transistor is connected with the level transmission output end of the n-j-1 level grid driving module; And the first end of the first capacitor is connected with the second end of the second transistor, and the second end of the first capacitor is connected with the first end of the first transistor.
  6. 6. The gate drive circuit of claim 5, wherein the enable control subunit comprises: A third transistor, a control terminal of which is connected to the state node, a first terminal of which is connected to the second control signal terminal, and a second terminal of which is connected to the enable node; and the first end of the second capacitor is connected with the level transmission output end of the n-j-3 level grid driving module, and the second end of the second capacitor is connected with the enabling node.
  7. 7. The gate drive circuit of claim 4 or 6, wherein the enable control subunit further comprises: And the control end of the fourth transistor is connected with the reset signal end, the first end of the fourth transistor is connected with the enabling node, and the second end of the fourth transistor is connected with the low level end.
  8. 8. The gate drive circuit of any of claims 2-6, wherein the gate switch subunit comprises: and the control end of the fifth transistor is connected with the enabling node, the first end of the fifth transistor is connected with the pre-charge control node, and the second end of the fifth transistor is connected with the driving control node.
  9. 9. The gate driving circuit according to claim 1, wherein, The precharge unit comprises a sixth transistor, wherein the control end of the sixth transistor is connected with the level transmission output end of the n-j level grid driving module, the first end of the sixth transistor is connected with the control end of the sixth transistor, and the second end of the sixth transistor is connected with the precharge control node; Or/and, the stage transmission unit comprises a seventh transistor and a third capacitor, wherein the control end of the seventh transistor is connected with the pre-charge control node, the first end of the seventh transistor is connected with the clock signal end of the current stage, and the second end of the seventh transistor is used as the stage transmission end of the gate driving module of the current stage; Or/and, the driving output unit comprises an eighth transistor and a fourth capacitor, wherein the control end of the eighth transistor is connected with the driving control node, the first end of the eighth transistor is connected with the clock signal end of the current stage, the second end of the eighth transistor is used as the driving output end of the current stage, the first end of the fourth capacitor is connected with the control end of the eighth transistor, and the second end of the fourth capacitor is connected with the second end of the eighth transistor.
  10. 10. The gate drive circuit of claim 1, wherein the nth stage gate drive module further comprises a pull-down unit configured to pull down the precharge control node and the drive output; wherein the pull-down unit includes: a control end of the ninth transistor is connected with a level transmission output end of the n+i level grid electrode driving module, a first end of the ninth transistor is connected with a driving output end of the driving output unit, and a second end of the ninth transistor is connected with a low level end; And a tenth transistor, wherein a control terminal of the tenth transistor is connected with a control terminal of the ninth transistor, a first terminal of the tenth transistor is connected with the precharge control node, and a second terminal of the tenth transistor is connected with the low level terminal.

Description

Gate driving circuit Technical Field The disclosure belongs to the technical field of display driving, and particularly relates to a gate driving circuit. Background With the increasing demands of display devices for large size, high resolution and low power consumption, progressive scanning using GOA (GATE DRIVER on Array) technology has become a mainstream driving method. In order to reduce the power consumption of the display device, a display mode of partial refresh is proposed, namely, only scanning is performed in a picture update area instead of refreshing the whole screen, thereby remarkably reducing the power consumption of GOA and driving IC. However, in the GOA circuit of the current local refresh, under the multi-CK architecture, due to the longer time sequence overlapping area between adjacent stage signals, erroneous output is usually generated at the edge of the refresh area, resulting in abnormal display, and the reliability of the local refresh is reduced. Therefore, how to improve the false output of the local refresh edge position is a current urgent problem to be solved. Disclosure of Invention The embodiment of the application provides a grid driving circuit, which is characterized in that a local brush control unit is arranged between a precharge unit and a driving output unit, and whether the driving output unit outputs a grid driving signal is dynamically controlled according to whether the current line is a refreshing line, so that the problem of false output of the local refreshing edge position is solved. The application provides a gate driving circuit which comprises N cascaded gate driving modules, wherein the nth-stage gate driving module comprises a pre-charging unit, a stage transmission unit and a local brushing control unit, wherein the pre-charging unit is connected with a pre-charging control node of the current stage and is configured to pre-charge the pre-charging control node through a stage transmission signal of the nth-j-stage gate driving module, the stage transmission unit is connected with the pre-charging control node and is configured to output a stage transmission signal of the current stage under the control of voltage on the pre-charging control node, the local brushing control unit is connected with the pre-charging control node and a driving control node of the current stage and is configured to control the pre-charging control node to be conducted with the driving control node if the current stage is a refresh line in a local refresh mode, and is configured to control the pre-charging control node to be disconnected with the driving control node if the current stage is a non-refresh line in a local refresh mode, and is configured to output a gate driving signal of the current stage under the control of the driving control node. Optionally, the local brushing control unit comprises a state response subunit, an enabling control subunit and a gating switch subunit, wherein the state response subunit is connected with a state node of a current stage and at least one control signal end and is configured to respond to the level state of the at least one control signal end to form a potential corresponding to a refreshing state of the current stage on the state node, the refreshing state comprises a refreshing row and a non-refreshing row, the enabling control subunit is connected with the state node and an enabling node of the current stage and is configured to output a corresponding driving enabling signal to the enabling node according to the potential on the state node, and the gating switch subunit is connected with the enabling node, the pre-charging control node and the driving control node and is configured to be controlled by the driving enabling signal on the enabling node to conduct or shut off the electric connection between the pre-charging control node and the driving control node. Optionally, the state response subunit comprises a first transistor, a second transistor, a first capacitor and a second capacitor, wherein the control end of the first transistor is connected with a first control signal end, the first end of the first transistor is connected with the state node, the second end of the first transistor is connected with a low level end, the control end of the second transistor is connected with a second control signal end, the first end of the second transistor is connected with a level transmission output end of an n-j level grid driving module, the first end of the first capacitor is connected with the second end of the second transistor, and the second end of the first capacitor is connected with the first end of the first transistor. Optionally, the enabling control subunit comprises a third transistor, wherein a control end of the third transistor is connected with the state node, a first end of the third transistor is connected with the second control signal end, and a second end of the third transistor is connected with the enablin