CN-121982996-A - Display substrate and display device

CN121982996ACN 121982996 ACN121982996 ACN 121982996ACN-121982996-A

Abstract

The disclosure provides a display substrate and a display device, and belongs to the technical field of display. The display substrate comprises a substrate, a grid driving circuit and a frame starting signal line, wherein the substrate is divided into a display area and a peripheral area positioned on at least one side of the display area, the grid driving circuit and the frame starting signal line are arranged on the substrate and positioned in the peripheral area, the frame starting signal line is configured to provide a frame starting signal for at least one shift register in the grid driving circuit, the frame starting signal line comprises at least two signal line segments which are arranged in a disconnecting mode, and a transfer electrode which is connected with the two signal line segments which are arranged adjacently, and the transfer electrode and the signal line segments are positioned on different layers.

Inventors

TIAN ZIHAN
CHENG LIANG
LIU XIN
JIANG PENG
DING JUN
HUANG JUNLING
WANG HUI
LIU JIANTAO

Assignees

武汉京东方光电科技有限公司
京东方科技集团股份有限公司

Dates

Publication Date: 20260505
Application Date: 20241031

Claims (18)

1. A display substrate, comprising: A substrate divided into a display area and a peripheral area positioned on at least one side of the display area; A gate driving circuit and a frame on signal line disposed on the substrate, in the peripheral region, the frame on signal line configured to supply a frame on signal to at least one shift register in the gate driving circuit, wherein, The frame opening signal line comprises at least two signal line segments which are arranged in a disconnected mode and a transfer electrode which is connected with the two signal line segments which are arranged adjacently, wherein the transfer electrode and the signal line segments are located in different layers.
2. The display substrate of claim 1, further comprising: the first conductive layer is arranged on the substrate base plate, and the grid electrode of each thin film transistor of the shift register is positioned on the first conductive layer; the first interlayer insulating layer is arranged on one side of the first conductive layer, which is away from the substrate base plate; The second conductive layer is arranged on one side, away from the first conductive layer, of the first interlayer insulating layer, and the source electrode and the drain electrode of each thin film transistor of the shift register are positioned on the second conductive layer; the second interlayer insulating layer is arranged on one side of the second conductive layer, which is away from the first interlayer insulating layer; The third conductive layer is arranged on one side, away from the second conductive layer, of the second interlayer insulating layer, and the common electrode of the pixel unit located in the display area is located on the third conductive layer.
3. The display substrate according to claim 2, wherein the transfer electrode comprises a first transfer portion, a second transfer portion and a third transfer portion, wherein the first transfer portion and the second transfer portion are positioned on the third conductive layer, the third transfer portion is positioned on the second conductive layer, and the first transfer portion and the second transfer portion are respectively connected with the third transfer portion through at least one first connection via hole and at least one second connection via hole, and the first connection via hole and the second connection via hole penetrate through the second interlayer insulating layer; The signal line segments are located on the first conductive layer, one of the signal line segments is connected with the first switching part through at least one third connecting via hole, the other signal line segment is connected with the second switching part through at least one fourth connecting via hole, and the third connecting via hole and the fourth connecting via hole penetrate through the first interlayer insulating layer and the second interlayer insulating layer.
4. A display substrate according to claim 3, wherein the orthographic projections of the third transition and the signal line segment on the substrate do not overlap, and the orthographic projection of one of the third transitions on the substrate is located between two adjacently disposed orthographic projections of the signal line segment on the substrate; For two adjacent signal line segments and a transfer electrode for connecting the two, wherein a third transfer part of the transfer electrode is provided with a first end part and a second end part which are oppositely arranged along the extending direction of the signal line segments, one signal line segment is provided with a third end part which is connected with the first end part of the third transfer part through the first transfer part, the other signal line segment is provided with a fourth end part which is connected with the second end part of the third transfer part through the second transfer part, the front projection of the first end part on the substrate is wider, the front projection of the second end part on the substrate is wider, the front projection of the third end part on the substrate is wider, and the front projection of the fourth end part on the substrate is wider.
5. The display substrate of claim 4, wherein an orthographic projection of a first connection via for connecting the third adapter and the first adapter on the substrate is covered by an orthographic projection of the first end on the substrate; an orthographic projection of a second connection via for connecting the third adapter and the second adapter on the substrate is covered by an orthographic projection of the second end on the substrate; The orthographic projection of the third connecting via hole used for connecting the signal line segment and the first switching part on the substrate is covered by the orthographic projection of the third end part on the substrate; orthographic projection of a fourth connecting via hole for connecting a signal line segment and the second transfer part on the substrate is covered by orthographic projection of the fourth end part on the substrate; The front projection of the first transfer part on the substrate covers the front projection of the first end part and the third end part on the substrate, and the front projection of the second transfer part on the substrate covers the front projection of the second end part and the fourth end part on the substrate.
6. The display substrate of claim 5, wherein the first connection via at which the first end is located is a plurality of first connection vias, and the plurality of first connection vias are arranged in a plurality of columns, the number of first connection vias in each column being positively correlated with a line width of the first end; the second connecting through holes at the position of the second end part are in a plurality, the second connecting through holes are arranged in a plurality of columns, and the number of the second connecting through holes in each column is positively related to the line width of the second end part; The third connecting through holes at the third end part are in a plurality, the third connecting through holes are arranged in a plurality of columns, and the number of the third connecting through holes in each column is positively related to the line width of the third end part; the number of the fourth connecting through holes at the position of the fourth end part is multiple, the fourth connecting through holes are arranged in multiple columns, and the number of the fourth connecting through holes in each column is positively related to the line width of the fourth end part.
7. The display substrate according to claim 3, wherein for two adjacently disposed signal line segments, one is connected to a third via through at least one fifth connection via, the other is connected to the third via through at least one sixth connection via, and the fifth connection via and the sixth connection via each penetrate through the first interlayer insulating layer.
8. The display substrate according to claim 7, wherein for two adjacently disposed signal line segments and a transfer electrode for connecting the two, wherein a third transfer portion of the transfer electrode has a first end portion and a second end portion disposed opposite to each other in an extending direction thereof, one of the signal line segments has a third end portion connected to the first end portion of the third transfer portion through the first transfer portion, and the other signal line segment has a fourth end portion connected to the second end portion of the third transfer portion through the second transfer portion; the orthographic projection of the first end part on the substrate plate covers the orthographic projection of the third end part on the substrate plate, and the orthographic projection of the second end part on the substrate plate covers the orthographic projection of the fourth end part on the substrate plate.
9. The display substrate of claim 8, wherein the fifth connection via is orthographic projected on the substrate within an area defined by orthographic projections of the first connection via and the third connection via on the substrate; The sixth connection via is orthographically projected on the substrate within an area defined by orthographically projection of the second connection via and the fourth connection via on the substrate.
10. The display substrate of claim 8, wherein the first end comprises a first expansion and a second expansion, the second end comprises a third expansion and the fourth expansion; The orthographic projections of the first expansion part and the second expansion part on the substrate are not overlapped with the orthographic projection of the third end part on the substrate, and the orthographic projections of the third expansion part and the fourth expansion part on the substrate are not overlapped with the orthographic projection of the fourth end part on the substrate; At least part of the first connecting through holes are overlapped with the orthographic projection of the first expansion parts on the substrate, and at least part of the first connecting through holes are overlapped with the orthographic projection of the second expansion parts on the substrate; At least part of the second connecting through holes are overlapped with the orthographic projection of the third expansion parts on the substrate, and at least part of the second connecting through holes are overlapped with the orthographic projection of the fourth expansion parts on the substrate.
11. The display substrate according to claim 3, wherein the transfer electrode further comprises a fourth transfer portion, the second transfer portion is located between the signal line segments adjacently disposed and connected with the third transfer portion through at least one seventh connection via, and the seventh connection via penetrates through the first interlayer insulating layer.
12. The display substrate of any one of claims 1-11, further comprising a redundant shift register located in the peripheral region; The redundant shift register comprises an input sub-circuit, an output sub-circuit, at least one pull-down control sub-circuit and at least one pull-down sub-circuit; The input sub-circuit is configured to respond to an input signal of a signal input end and precharge a pull-up node through the input signal; The output sub-circuit is configured to respond to the potential of the pull-up node and output a clock signal through a signal output end; The output sub-circuit is configured to respond to the potential of the pull-up node and output a clock signal through a cascade signal terminal; The pull-down control sub-circuit is configured to respond to a power supply voltage and control the potential of a pull-down node through the power supply voltage, and one pull-down control sub-circuit is connected with one pull-down sub-circuit and one pull-down sub-circuit, and the connection node between the pull-down control sub-circuit and the pull-down sub-circuit is the pull-down node; The pull-down subcircuit is configured to pull down the potential of the pull-down node by a non-operating level signal in response to the potential of the pull-up node.
13. The display substrate of claim 12, wherein the output sub-circuit comprises a third transistor and a storage capacitor; The first end of the storage capacitor is connected with the grid electrode of the third transistor, the second end of the storage capacitor is connected with the drain electrode of the third transistor, and at least one of the source electrode and the drain electrode of the third transistor is connected with the frame starting signal line.
14. The display substrate of claim 12, wherein the output sub-circuit comprises a third transistor and a storage capacitor; the first end of the storage capacitor is connected with the grid electrode of the third transistor, the second end of the storage capacitor is connected with the drain electrode of the third transistor, at least one of the source electrode and the drain electrode of the third transistor is connected with the first tip structure, and the frame starting signal line is connected with the second tip structure; the tips of the first tip structures are opposite to the tips of the second tip structures; Or alternatively The first tip structure comprises a first main body part and at least one first tip part connected to one side of the extending direction of the first main body part, the second tip structure comprises a second main body part and at least one second tip part connected to one side of the extending direction of the second main body part, and the first tip part and the second tip part are opposite to each other one by one.
15. The display substrate of claim 12, wherein the pull-down control sub-circuit comprises a fifth transistor and a ninth transistor; The grid electrode of the fifth transistor is connected with the drain electrode of the ninth transistor and the source electrode of the eighth transistor, the source electrode of the fifth transistor is connected with the power supply voltage end and the grid electrode of the ninth transistor, and the drain electrode of the fifth transistor is connected with the pull-down node; A grid electrode of the sixth transistor is connected with the grid electrode of the eighth transistor and the pull-up node, and a source electrode of the sixth transistor is connected with the pull-down node; the drain electrode of the sixth transistor and the drain electrode of the eighth transistor are both connected with a non-working level signal end; the frame on signal line is connected to a source of the eighth transistor, and/or the frame on signal line is connected to a gate of the sixth transistor.
16. The display substrate of claim 12, wherein the pull-down control sub-circuit comprises a fifth transistor and a ninth transistor; The grid electrode of the fifth transistor is connected with the drain electrode of the ninth transistor and the source electrode of the eighth transistor, the source electrode of the fifth transistor is connected with the power supply voltage end and the grid electrode of the ninth transistor, and the drain electrode of the fifth transistor is connected with the pull-down node; A grid electrode of the sixth transistor is connected with the grid electrode of the eighth transistor and the pull-up node, and a source electrode of the sixth transistor is connected with the pull-down node; the drain electrode of the sixth transistor and the drain electrode of the eighth transistor are both connected with a non-working level signal end; one of a source of the eighth transistor and a gate of the sixth transistor is connected to a first tip structure, and the frame on signal line is connected to a second tip structure; the tips of the first tip structures are opposite to the tips of the second tip structures; Or alternatively The first tip structure comprises a first main body part and at least one first tip part connected to one side of the extending direction of the first main body part, the second tip structure comprises a second main body part and at least one second tip part connected to one side of the extending direction of the second main body part, and the first tip part and the second tip part are opposite to each other one by one.
17. The display substrate of any one of claims 1-11, further comprising a redundant clock signal line, the frame on signal line being connected to the redundant clock signal line.
18. A display device comprising the display substrate of any one of claims 1-17.

Description

Display substrate and display device Technical Field The disclosure belongs to the technical field of display, and particularly relates to a display substrate and a display device. Background In the process of manufacturing a TFT-LCD (Thin Film Transistor Liquid CRYSTAL DISPLAY thin film transistor liquid crystal display), electrostatic charges are accumulated on a substrate due to various factors such as equipment, power-up in a detection process, and external environment. When the charge on the substrate accumulates to a certain peak, it causes electrostatic discharge (Electro-STATIC DISCHARGE, ESD). Such discharge typically produces a strong discharge current which is likely to damage components in the circuit, resulting in poor display devices. The peripheral area of the current multi-type TFT-LCD product is provided with a gate driving electrode, wherein the gate driving electrode includes a plurality of cascaded shift registers, and typically, the signal input end of the first shift register is connected to a frame on signal line. Because the frame is opened the signal line singlely, discharge path is few, easily produces ESD and causes hole structure and GOA (Gate on Array) unit to burn, causes the screen display to appear unusual. Disclosure of Invention The invention aims to at least solve one of the technical problems in the prior art and provides a display substrate and a display device. Embodiments of the present disclosure provide a display substrate, including: A substrate divided into a display area and a peripheral area positioned on at least one side of the display area; A gate driving circuit and a frame on signal line disposed on the substrate, in the peripheral region, the frame on signal line configured to supply a frame on signal to at least one shift register in the gate driving circuit, wherein, The frame opening signal line comprises at least two signal line segments which are arranged in a disconnected mode and a transfer electrode which is connected with the two signal line segments which are arranged adjacently, wherein the transfer electrode and the signal line segments are located in different layers. Wherein, the display substrate further includes: the first conductive layer is arranged on the substrate base plate, and the grid electrode of each thin film transistor of the shift register is positioned on the first conductive layer; the first interlayer insulating layer is arranged on one side of the first conductive layer, which is away from the substrate base plate; The second conductive layer is arranged on one side, away from the first conductive layer, of the first interlayer insulating layer, and the source electrode and the drain electrode of each thin film transistor of the shift register are positioned on the second conductive layer; the second interlayer insulating layer is arranged on one side of the second conductive layer, which is away from the first interlayer insulating layer; The third conductive layer is arranged on one side, away from the second conductive layer, of the second interlayer insulating layer, and the common electrode of the pixel unit located in the display area is located on the third conductive layer. The transfer electrode comprises a first transfer part, a second transfer part and a third transfer part, wherein the first transfer part and the second transfer part are positioned on the third conductive layer, the third transfer part is positioned on the second conductive layer, and the first transfer part and the second transfer part are respectively connected with the third transfer part through at least one first connection via hole and at least one second connection via hole; The signal line segments are located on the first conductive layer, one of the signal line segments is connected with the first switching part through at least one third connecting via hole, the other signal line segment is connected with the second switching part through at least one fourth connecting via hole, and the third connecting via hole and the fourth connecting via hole penetrate through the first interlayer insulating layer and the second interlayer insulating layer. The second transfer part and the signal line segment are not overlapped on the front projection of the second transfer part on the substrate, and the front projection of one second transfer part on the substrate is positioned between two adjacent front projections of the signal line segment on the substrate; For two adjacent signal line segments and a transfer electrode for connecting the two, wherein a third transfer part of the transfer electrode is provided with a first end part and a second end part which are oppositely arranged along the extending direction of the signal line segments, one signal line segment is provided with a third end part which is connected with the first end part of the third transfer part through the first transfer part, the other signal line segment is provided with