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CN-121983095-A - DDR5 temperature-voltage cooperative self-adaptive gate driving regulation and control method, equipment and medium

CN121983095ACN 121983095 ACN121983095 ACN 121983095ACN-121983095-A

Abstract

The invention discloses a DDR5 temperature-voltage cooperative self-adaptive gate driving regulation and control method, equipment and medium, relating to the technical field of gate driving regulation and control, comprising the steps of acquiring the current working temperature and the current working voltage of a memory chip in real time; the method comprises the steps of taking the current working temperature and the current working voltage as joint input key values, inquiring a predefined driving strength lookup table, mapping to obtain corresponding driving strength configuration values, wherein the driving strength lookup table records mapping relations between different temperature-voltage combinations and optimal driving strength configuration values, generating driving strength control signals according to the driving strength configuration values, and dynamically adjusting driving strength of a data output driver in a memory chip based on the driving strength control signals. The invention dynamically adjusts the driving strength of the data output driver based on the predefined mapping relation by cooperatively sensing the working temperature and the power supply voltage of the memory chip in real time, thereby effectively overcoming the defect that the static configuration method cannot adapt to the dynamic change of the environment.

Inventors

  • JIN CHUNYU
  • ZHAN JIANPING
  • ZHANG WEILONG

Assignees

  • 成都芯忆联信息技术有限公司

Dates

Publication Date
20260505
Application Date
20260122

Claims (10)

  1. 1. The DDR5 temperature-voltage cooperative self-adaptive gate driving regulation and control method is characterized by being applied to a memory chip and comprising the following steps of: s1, acquiring the current working temperature and the current working voltage of the memory chip in real time; S2, inquiring a predefined driving strength lookup table by taking the current working temperature and the current working voltage as joint input key values, and mapping to obtain corresponding driving strength configuration values, wherein the driving strength lookup table records mapping relations between different temperature-voltage combinations and optimal driving strength configuration values; S3, generating a driving strength control signal according to the driving strength configuration value, and dynamically adjusting the driving strength of the data output driver in the memory chip based on the driving strength control signal.
  2. 2. The DDR5 temperature-voltage cooperative adaptive gate drive regulation method of claim 1, wherein prior to performing S2, the drive strength lookup table is pre-established by: in the chip design stage, determining a plurality of different temperature working points and a plurality of different voltage working points; For each temperature-voltage combination working point formed by the temperature working point and the voltage working point, determining a driving strength value which can meet the signal integrity requirement and has the lowest power consumption under the temperature-voltage combination working point through signal integrity simulation or actual test; And establishing a mapping relation between each temperature-voltage combination working point and the determined corresponding driving intensity value, and storing the mapping relation as the content of the driving intensity lookup table.
  3. 3. The method of claim 1, wherein steps S1, S2 and S3 are periodically performed by a control logic unit within the memory chip at predetermined fixed time intervals.
  4. 4. The DDR5 temperature-voltage cooperative adaptive gate drive control method according to claim 1, wherein steps S2 and S3 are performed when a trigger condition is satisfied, the trigger condition being determined based on the current operation parameter acquired in step S1; The triggering condition is that the absolute value of the current working temperature of the memory chip relative to the change amount of the working temperature recorded in the last execution of the step S3 exceeds a first preset threshold value, or the absolute value of the current working voltage of the memory chip relative to the change amount of the working voltage recorded in the last execution of the step S3 exceeds a second preset threshold value.
  5. 5. The DDR5 temperature-voltage collaborative adaptive gate drive control method according to claim 1, wherein the dynamically adjusting the drive strength of the data output driver in the memory chip based on the drive strength control signal comprises: According to the driving strength configuration value, rewriting a field for configuring driving strength in a mode register in the memory chip; The data output driver comprises a plurality of driving units connected in parallel, and the on-off of each driving unit is controlled by the value of the corresponding bit in the mode register; by rewriting the field value of the mode register, the number or equivalent size of the cells in the on state in the plurality of parallel driving cells is changed, thereby changing the total equivalent output impedance of the data output driver linearly or stepwise.
  6. 6. The DDR5 temperature-voltage cooperative adaptive gate drive control method of claim 1, wherein said drive strength lookup table is stored solidified in a ROM inside said memory chip; In S2, inquiring the driving strength lookup table comprises splicing the digitalized codes of the current working temperature and the current working voltage to form an access address, and reading data of corresponding storage positions in the ROM by using the access address as the driving strength configuration value.
  7. 7. The DDR5 temperature-voltage collaborative adaptive gate drive control method according to claim 1, wherein the drive strength lookup table is generated by a set of combinational logic circuits inside the memory chip in real-time computation; in S2, inquiring the driving strength lookup table comprises the steps of inputting the digitalized codes of the current working temperature and the current working voltage into the combinational logic circuit, and directly outputting the corresponding driving strength configuration value by the combinational logic circuit according to a preset logic operation rule.
  8. 8. The DDR5 temperature-voltage collaborative adaptive gate driving adjustment and control method according to any one of claims 1 to 7, wherein in S1, the current operation temperature is obtained in real time by reading an output of a digital temperature sensor for a temperature refresh function inside the memory chip, and the current operation voltage is obtained in real time by reading an output of a voltage analog-to-digital converter in a power management unit inside the memory chip.
  9. 9. A computer device, characterized in that it comprises a memory on which a computer program is stored and a processor which, when executing the computer program, implements the method according to any of claims 1-7.
  10. 10. A computer readable storage medium, characterized in that the storage medium stores a computer program which, when executed by a processor, implements the method according to any of claims 1-7.

Description

DDR5 temperature-voltage cooperative self-adaptive gate driving regulation and control method, equipment and medium Technical Field The invention relates to the technical field of gate drive regulation and control, in particular to a DDR5 temperature-voltage cooperative self-adaptive gate drive regulation and control method, device and medium. Background In current DDR5 memory technology, the drive strength of the data output drivers is typically configured by a mode register. The configuration process of the mode register is generally completed in a system start initialization stage, and the memory controller realizes one-time setting by writing a mode register command and keeps static unchanged in the following whole running period. The inventor researches and discovers that the environmental factors faced by the memory chip in actual work are in continuous dynamic change. The chip junction temperature can change along with fluctuation of the calculation load, and meanwhile, the power supply voltage can also be influenced by power supply noise and load transient to generate fluctuation. This static configuration is difficult to adapt to the dynamically changing operating conditions described above, and has significant drawbacks. When the MOS FET is at the high temperature and low voltage operating point, the carrier mobility of the MOS FET is reduced, which results in the deterioration of the driving capability of the driver, and further causes the problems of reduced signal edge rate, closed data eye, and wrong timing. Further, under the working conditions of low temperature and high voltage, the driving capability of the driver is relatively too strong, which is easy to cause signal overshoot, undershoot and ringing phenomena to be aggravated, thus not only causing unnecessary power consumption waste, but also bringing serious electromagnetic interference. In order to ensure that the system can still reliably operate under various extreme working conditions, the prior art scheme is often forced to adopt a conservative strategy, namely, a higher driving strength value is preset in a mode register. The strategy causes the memory chip to be in a state with over-high driving strength under most normal working conditions, so that not only is the energy efficiency performance of the system sacrificed, but also the signal quality is negatively influenced, and the method is a passive and low-efficiency design method in essence. Disclosure of Invention The embodiment of the invention provides a DDR5 temperature-voltage cooperative self-adaptive gate drive regulation and control method, equipment and medium, and aims to solve the technical problem of providing an effective solution capable of adaptively regulating gate drive strength in real time according to dynamic changes of working environments so as to optimize signal integrity, timing margin and system power consumption. In a first aspect, an embodiment of the present invention provides a DDR5 temperature-voltage cooperative adaptive gate driving adjustment method, applied to a memory chip, including: s1, acquiring the current working temperature and the current working voltage of the memory chip in real time; S2, inquiring a predefined driving strength lookup table by taking the current working temperature and the current working voltage as joint input key values, and mapping to obtain corresponding driving strength configuration values, wherein the driving strength lookup table records mapping relations between different temperature-voltage combinations and optimal driving strength configuration values; S3, generating a driving strength control signal according to the driving strength configuration value, and dynamically adjusting the driving strength of the data output driver in the memory chip based on the driving strength control signal. Optionally, before performing S2, the driving strength lookup table is pre-established by: in the chip design stage, determining a plurality of different temperature working points and a plurality of different voltage working points; For each temperature-voltage combination working point formed by the temperature working point and the voltage working point, determining a driving strength value which can meet the signal integrity requirement and has the lowest power consumption under the temperature-voltage combination working point through signal integrity simulation or actual test; And establishing a mapping relation between each temperature-voltage combination working point and the determined corresponding driving intensity value, and storing the mapping relation as the content of the driving intensity lookup table. Optionally, steps S1, S2 and S3 are periodically performed by a control logic unit inside the memory chip at preset fixed time intervals. Optionally, steps S2 and S3 are performed when a trigger condition is satisfied, the trigger condition being determined based on the current operating parameter obtaine