CN-121983096-A - Semiconductor structure, preparation method thereof and electronic equipment

Abstract

The application relates to a semiconductor structure, a preparation method thereof and electronic equipment, and relates to the technical field of semiconductors. The semiconductor structure comprises a memory cell, wherein the memory cell comprises a ferroelectric memory module and a read module. The ferroelectric memory module includes a write transistor and a ferroelectric capacitor. The read module includes a read transistor. The write transistor includes a first gate connected to a write word line and a first semiconductor layer connected to a write bit line. The ferroelectric capacitor includes a first electrode connected to the first semiconductor layer, a second electrode connected to the read scan line, and a ferroelectric layer between the first electrode and the second electrode. The read transistor includes a second gate electrode connected to the first electrode, and a second semiconductor layer connected to the source line and the read bit line, respectively. The write transistor is used for writing data to the ferroelectric capacitor, and the read transistor is used for nondestructively reading data stored in the ferroelectric capacitor. The application can effectively improve the durability of the device under the condition of ensuring the nonvolatile memory.

Inventors

• DONG SHUCHENG
• Lv Haochang
• LI GENGFEI
• DONG BOWEN
• WANG GUILEI

Assignees

• 北京超弦存储器研究院

Dates

Publication Date

20260505

Application Date

20241031

Claims (15)

1. 1. The semiconductor structure is characterized by comprising at least one memory cell, wherein the memory cell comprises a ferroelectric memory module and a reading module; the ferroelectric memory module includes: A write transistor including a first gate connected to a write word line, and a first semiconductor layer connected to a write bit line; a ferroelectric capacitor including a first electrode connected to the first semiconductor layer, a second electrode connected to a read scan line, and a ferroelectric layer between the first electrode and the second electrode; The read module includes: the read transistor comprises a second grid electrode connected with the first electrode and a second semiconductor layer respectively connected with a source line and a read bit line; wherein the write transistor is for writing data to the ferroelectric capacitor, and the read transistor is for nondestructively reading the data stored in the ferroelectric capacitor.
2. 2. The semiconductor structure of claim 1, wherein a plurality of the memory cell arrays are stacked and arranged in columns along a first direction perpendicular to the substrate and rows along a second direction parallel to the substrate, the semiconductor structure further comprising: the write bit lines extend along the second direction, and one write bit line is connected with the first semiconductor layer of one row of the memory cells; the writing lines extend along the first direction, and one writing line is connected with the first grid electrode of one column of the memory cells; The first semiconductor layer is insulated around the outside of the first gate of the same write transistor.
3. 3. The semiconductor structure of claim 2, wherein the first electrode and the corresponding second gate electrode each extend along and are connected in a third direction parallel to the substrate, the third direction intersecting the second direction; one end of the first electrode, which is far away from the second grid electrode, is connected with the first semiconductor layer of the same ferroelectric memory module; The ferroelectric layer and the second electrode are laminated around the outer side of the first electrode; the semiconductor structure further includes: the plurality of read scanning lines extend along the first direction, and one read scanning line is connected with the second electrode of one row of the memory cells.
4. 4. The semiconductor structure of claim 3, wherein the first electrode and the corresponding second gate are a unitary structure.
5. 5. The semiconductor structure of claim 3, wherein the second semiconductor layer insulates and covers an end surface of the second gate away from the first electrode and a sidewall of the second gate in the same read transistor, the semiconductor structure further comprising: the read bit lines extend along the second direction, and one read bit line is connected with the second semiconductor layers of one row of the memory cells and is positioned at one side of the second semiconductor layers, which is away from the end surface of the second grid electrode; the source electrode line is positioned on one side of the second semiconductor layer, which is away from the side wall of the second grid electrode, and is connected with the second semiconductor layer of each memory cell positioned in the same column and the same row.
6. 6. The semiconductor structure of any one of claims 1-5, wherein the source line is grounded.
7. 7. A method of fabricating a semiconductor structure, comprising: providing a substrate, and forming a stacked structure on the substrate, wherein the stacked structure comprises a plurality of first dielectric layers and a plurality of second dielectric layers which are alternately stacked; Forming an etching hole penetrating through the stacked structure along a first direction perpendicular to the substrate; The second dielectric layer is etched based on the etching holes, and a first accommodating groove is formed in the second dielectric layer, wherein the first accommodating groove extends along a third direction parallel to the substrate and comprises a first area, a second area and a third area which are distributed in sequence in the third direction; forming a second semiconductor layer, a second dielectric layer and a second gate of the read transistor in the third region; forming a first electrode of a ferroelectric capacitor in the second region; Forming a first semiconductor layer, a first dielectric layer and a first grid electrode of the write transistor in an inner layer in the first area; Forming a first etching groove penetrating the stacking structure and at least partially exposing the first electrode; Removing the first dielectric layer between adjacent first electrodes based on the first etching grooves; Forming a ferroelectric medium layer and a second electrode of the ferroelectric capacitor based on the first etching groove and the removing area of the first medium layer, wherein the ferroelectric medium layer coats the first electrode, and the second electrode coats the ferroelectric medium layer; the memory cell comprises a ferroelectric memory module and a reading module, wherein the ferroelectric memory module comprises the writing transistor and the ferroelectric capacitor, the reading module comprises the reading transistor, the writing transistor is used for writing data into the ferroelectric capacitor, and the reading transistor is used for nondestructively reading the data stored in the ferroelectric capacitor.
8. 8. The method of manufacturing a semiconductor structure according to claim 7, wherein before forming the etched hole through the stacked structure, the method further comprises: Etching the stacked structure to form a plurality of first isolation grooves which are arranged at intervals in a second direction parallel to the substrate, wherein the second direction intersects with the third direction; forming a first isolation structure in the first isolation groove; Etching the stacking structure to form second isolation grooves at two ends of the first isolation structure in the third direction respectively, wherein the second isolation grooves penetrate through the stacking structure along the first direction and extend along the second direction; Etching the second dielectric layer based on the second isolation groove, and forming a writing bit line accommodating groove and a reading bit line accommodating groove at two ends of the first isolation structure in the third direction respectively; Forming a writing bit line in the writing bit line accommodating groove and forming a reading bit line in the reading bit line accommodating groove; forming a second isolation structure in the second isolation groove; The etching holes are formed between two adjacent first isolation structures and between the writing bit line and the reading bit line, two ends of the first accommodating groove in the third direction are respectively exposed out of the writing bit line and the reading bit line, the second semiconductor layer is connected with the reading bit line, and the first semiconductor layer is connected with the writing bit line.
9. 9. The method of manufacturing a semiconductor structure according to claim 8, wherein after the second semiconductor layer, the second dielectric layer, and the second gate electrode of the read transistor are formed by being stacked in the third region, the method further comprises: Forming a second etching groove penetrating the first isolation structure and at least partially exposing the second semiconductor layer; Removing the first dielectric layer between the adjacent second semiconductor layers based on the second etching grooves; and forming a source line connected with the second semiconductor layer in the second etching groove and the removing area of the first dielectric layer.
10. 10. The method of manufacturing a semiconductor structure according to claim 8, wherein forming the ferroelectric layer and the second electrode of the ferroelectric capacitor based on the first etching groove and the removed region of the first dielectric layer comprises: Forming a ferroelectric dielectric material layer, a second electrode material layer and a first supporting layer in the first etching groove and the removing area of the first dielectric layer in an inner layer manner, wherein the ferroelectric dielectric material layer surrounds and covers the side wall of the first electrode; forming third etching grooves penetrating through the first isolation structures and exposing the ferroelectric dielectric material layer at two ends of the first etching grooves in the third direction; Etching the ferroelectric dielectric material layer and the second electrode material layer along the third direction based on the third etching groove until the first supporting layer is exposed, so that the reserved ferroelectric dielectric material layer forms the ferroelectric dielectric layer, and the reserved second electrode material layer forms the second electrode; And forming a second supporting layer in the third etching groove.
11. 11. The method of manufacturing a semiconductor structure according to claim 7, wherein the forming a second semiconductor layer, a second dielectric layer, and a second gate electrode of the read transistor in the third region includes: forming a second semiconductor material layer, a second dielectric material layer and a sacrificial material layer in a lamination manner on the inner wall of the first accommodating groove and the inner wall of the etching hole; Removing the sacrificial material layer, the second dielectric material layer and the second semiconductor material layer in the first region and the second region based on the etching holes to form a sacrificial layer, a second dielectric layer and a second semiconductor layer in the third region, wherein the distance from the exposed end face of the sacrificial layer to the etching holes is smaller than the distance from the exposed end face of the second semiconductor layer to the etching holes; Forming a first insulating layer covering the exposed end surfaces of the second semiconductor layer, the second dielectric layer and the sacrificial layer; Etching the first insulating layer until the end face of the sacrificial layer is exposed; and removing the sacrificial layer, and forming the second grid electrode in the removed area of the sacrificial layer.
12. 12. The method of claim 11, wherein the first electrode and the second gate electrode are integrally formed in the same step using the same conductive material.
13. 13. The method of manufacturing a semiconductor structure according to claim 7, wherein the forming a first semiconductor layer, a first dielectric layer, and a first gate electrode of a write transistor in the first region includes: Forming a first semiconductor material layer, a first dielectric material layer and a first grid material layer in a lamination manner on the first region and the inner wall of the etching hole; Etching to remove the first gate material layer, the first dielectric material layer and the first semiconductor material layer on the inner wall of the etching hole, so that the first gate material layer reserved in the first area forms the first gate, the first dielectric material layer reserved in the first area forms the first dielectric layer, and the first semiconductor material layer reserved in the first area forms the first semiconductor layer, wherein the distance from the exposed end face of the first gate to the etching hole is smaller than the distance from the exposed end face of the first semiconductor layer to the etching hole; forming a second insulating layer covering the exposed end surfaces of the first semiconductor layer, the first dielectric layer and the first grid electrode; and etching the second insulating layer until the end face of the first grid electrode is exposed.
14. 14. The method of claim 13, wherein after etching the second insulating layer to expose the end surface of the first gate, the method further comprises: And forming a writing line connected with the first grid electrode in the etching hole.
15. 15. An electronic device comprising a semiconductor structure according to any one of claims 1 to 6 or a semiconductor structure manufactured by a method for manufacturing a semiconductor structure according to any one of claims 7 to 14.

Description

Semiconductor structure, preparation method thereof and electronic equipment Technical Field The present application relates to the field of semiconductor technologies, and in particular, to a semiconductor structure, a method for manufacturing the semiconductor structure, and an electronic device. Background Ferroelectric memories use the polarization state of a ferroelectric material to represent and store information, with different polarization directions representing different memory states. Ferroelectric memories have non-volatile properties, i.e. they retain stored data after power is turned off. However, since the reading process thereof requires turning the polarization direction a plurality of times while being realized by inducing charge change during the reading process, the polarization direction needs to be changed during the reading process, thus posing a great challenge in terms of durability and performance stability. Disclosure of Invention Based on the above, the application provides a semiconductor structure capable of effectively improving the durability of a device under the condition of ensuring the nonvolatile property of a memory, a preparation method thereof and electronic equipment. In a first aspect, an embodiment of the present application provides a semiconductor structure including at least one memory cell including a ferroelectric memory module and a read module. The ferroelectric memory module includes a write transistor and a ferroelectric capacitor. The read module includes a read transistor. The write transistor includes a first gate connected to a write word line, and a first semiconductor layer connected to a write bit line. The ferroelectric capacitor includes a first electrode connected to the first semiconductor layer, a second electrode connected to a read scan line, and a ferroelectric layer between the first electrode and the second electrode. The read transistor includes a second gate electrode connected to the first electrode, and a second semiconductor layer connected to a source line and a read bit line, respectively. Wherein the write transistor is for writing data to the ferroelectric capacitor, and the read transistor is for nondestructively reading the data stored in the ferroelectric capacitor. In some embodiments of the application, the plurality of memory cell arrays are stacked and arranged in columns along a first direction perpendicular to the substrate and in rows along a second direction parallel to the substrate. The semiconductor structure further includes a plurality of write bit lines and a plurality of write word lines. The write bit lines extend in a second direction, and one write bit line is connected to the first semiconductor layer of one row of memory cells. The write word lines extend along a first direction, and one write word line is connected with a first grid electrode of a column of memory cells. The first semiconductor layer is insulated around the outer side of the first gate of the same writing transistor. In some embodiments of the application, the first electrode and the corresponding second gate electrode each extend and are connected along a third direction parallel to the substrate, the third direction intersecting the second direction. One end of the first electrode, which is far away from the second grid electrode, is connected with the first semiconductor layer of the same ferroelectric memory module, and the write bit line is positioned on one side of the first semiconductor layer, which is far away from the first electrode. The ferroelectric layer and the second electrode are laminated around the outside of the first electrode. The semiconductor structure further includes a plurality of read scan lines. The read scan lines extend along the first direction, and one read scan line is connected with the second electrodes of one row of the memory cells. In some embodiments of the present application, the first electrode and the corresponding second gate electrode are of unitary construction. In some embodiments of the present application, the second semiconductor layer insulates and covers an end surface of the second gate electrode far from the first electrode and a side wall of the second gate electrode in the same read transistor. The semiconductor structure further includes a plurality of read bit lines and at least one source line. The read bit lines extend along the second direction, and one read bit line is connected with the second semiconductor layers of one row of the memory cells and is positioned at one side of the second semiconductor layers, which is away from the end face of the second grid electrode. The source line is located at one side of the second semiconductor layer away from the side wall of the second gate electrode and is connected with the second semiconductor layer of each memory cell located in the same column and the same row. In some embodiments of the application, the source line is grounded.