CN-121983097-A - Satellite-borne anti-fuse FPGA reinforcement protection method for avoiding PIN switch high-power switching damage

CN121983097ACN 121983097 ACN121983097 ACN 121983097ACN-121983097-A

Abstract

The invention discloses a satellite-borne anti-fuse FPGA reinforcement protection method for avoiding PIN switch high-power switching damage, which comprises the following steps that an original control signal is generated through an SRAM type FPGA, the pulse width of the original control signal is at least the sum of the maximum switch switching time delay delta t1, the radio frequency transmission and stabilization time delta t2, the design margin delta t3 and the time of an effective switching window delta t4, and the original control signal is used for obtaining a DA turn-off signal and an effective window signal in the anti-fuse FPGA. The method utilizes a high-reliability scheme realized by the satellite-borne anti-fuse FPGA, and can ensure that the electronic switch is not burnt out due to switching of various reasons when the power amplifier outputs high power. The method has strong universality, particularly solves the problems of the weight and the power consumption of the radio frequency front end of the integrated high-power base station in the design of high-integration products such as deep space exploration, and has wide application prospect.

Inventors

LIU MINGYANG
ZHANG SIHAN
WANG QIANQIONG
HE ZHIYING
TIAN JIA
ZHANG YUEPENG

Assignees

西安空间无线电技术研究所

Dates

Publication Date: 20260505
Application Date: 20251230

Claims (9)

1. A satellite-borne anti-fuse FPGA reinforcement protection method for avoiding high-power switching damage of a PIN switch is characterized by comprising the following steps: Generating an original control signal through an SRAM type FPGA, wherein the pulse width of the original control signal is at least the sum of the maximum time delay delta t1 of switching, the radio frequency transmission and stabilization time delta t2, the design margin delta t3 and the time of an effective switching window delta t 4; The original control signal obtains a DA turn-off signal and an effective window signal in an anti-fuse FPGA; the DA off signal is used for turning off the input signal of the DA device for a period of time; The effective window signal cuts off or connects the latch, so that the electronic switch control signal sent by the SRAM type FPGA in the effective window signal can be sent to the electronic switch driving circuit, and the control signal sent by the SRAM type FPGA outside the gate control signal can not be sent to the electronic switch driving circuit.
2. The reinforcement protection method for the satellite-borne anti-fuse FPGA for avoiding the high-power switching damage of the PIN switch according to claim 1, wherein the effective window signal is a signal with strictly limited pulse width obtained according to an original control signal and is used for enabling an LE PIN by a latch, so that an input signal of the latch in the pulse width of the effective window signal normally passes and an input signal outside the pulse width of the window signal cannot pass.
3. The method for reinforcing and protecting the FPGA of the satellite-borne antifuse for avoiding PIN-switched high-power switching damage according to claim 1, wherein the obtaining of the maximum delay of switching comprises: The maximum power amplifier shutdown time delta t-RFoff, the maximum power amplifier time delta t-RFon and the steady-state establishment time delta t-switch of the electronic switch related to hardware are required to be obtained; the maximum delay of switching is Δt1, Δt1=max [ Δt_rfoff, Δt_rfon, Δt_switch ].
4. The reinforcement protection method for the satellite-borne anti-fuse FPGA for avoiding PIN switch high-power switching damage according to claim 1 or 2, wherein the design margin needs to consider a minimum processing clock period and an extra margin protection of the processor, the processing rate of the anti-fuse FPGA processor is higher than 1MHz, the clock period is 1us, the extra margin protection is 0.5us, and 1.5us is selected as the design margin.
5. The reinforcement protection method for the satellite-borne anti-fuse FPGA for avoiding PIN switch high-power switching damage according to claim 1 or 2, wherein the effective switching window is generated by the anti-fuse FPGA, the minimum processing clock period of the processor is considered, the processing rate of the anti-fuse FPGA processor is higher than 1MHz, the clock period is 1us, and the minimum effective switching window is one clock period, namely 1us.
6. The reinforcement and protection method for the satellite-borne antifuse FPGA to avoid PIN switch high-power switching damage according to claim 1 or 2, wherein the acquisition of the rf transmission and stabilization time is based on the larger of the time delays from the DA to the power on/off of the switch 2 to the power on/off of the switch 1 output, to obtain the rf transmission and stabilization time Δt2.
7. The reinforcement protection method for the satellite-borne antifuse FPGA for avoiding PIN switch high-power switching damage according to claim 1or2, wherein the "original control signal" has a high level in the width and a low level outside the width.
8. The reinforcement protection method for the satellite-borne antifuse FPGA for avoiding PIN switch high-power switching damage according to claim 1 or 2, wherein the specific method for obtaining the DA off signal according to the original control signal is as follows: the anti-fuse FPGA samples an original control signal, and achieves delay of Deltat 1 time through internal logic to obtain a DA turn-off signal which achieves turn-off of an input signal of an external DA device for a period of time.
9. The method for reinforcing and protecting the FPGA of the satellite-borne antifuse for avoiding high-power switching damage of a PIN switch according to claim 1 is characterized in that an effective window signal is generated according to an original control signal, the front edge of the window signal is delayed by delta t < 1+ > delta t < 2 >, the width of the window signal lasts for delta t < 3+ > delta t <4 >, and the effective window signal is used for enabling PINs of a latch so that signals in the window normally pass and signals outside the window cannot pass.

Description

Satellite-borne anti-fuse FPGA reinforcement protection method for avoiding PIN switch high-power switching damage Technical Field The invention belongs to the field of communication product design, and particularly relates to a satellite-borne anti-fuse FPGA reinforcement protection method for avoiding high-power switching damage of a PIN switch. Background In the future deep space exploration task of China, the construction requirement of the extraterrestrial base station is met, an extraterrestrial mobile networking communication system needs to be built, and the development of a communication base station in the networking system is realized. Limited by rocket carrying capacity and the like, engineering implementation needs to face extremely severe restrictions on factors such as weight, power consumption and the like, and how to adopt a base station product scheme which is miniaturized and light as much as possible becomes the most core factor for restricting task success and failure. A typical scenario for such tasks is to consider the establishment of a communication network supporting more than about 10 communication nodes for supporting the transmission of intra-network device pictures, voice, remote telemetry, images, etc. traffic. The traditional ground base station scheme is continuously optimized from 3G, 4G, LTE G to 5G for many years, and a mature architecture which is serialized, produced and continuously evolved is formed. Ground base stations typically require large power amplification equipment to be deployed in order to maximize coverage distance. Meanwhile, in order to achieve 360-degree omni-directional coverage, communication of a plurality of cells needs to be met, and each antenna needs to be provided with an independent radio frequency front end RRU and an independent digital processing board card so as to achieve coverage of the plurality of cells. This solution typically requires the entire floor room support, as well as the consumption of kilowatts of power. The engineering costs that can be borne by deep space tasks are far exceeded, both in terms of weight and power consumption. In order to solve the development of communication base station equipment in the current-stage external base station construction of China, a satellite-borne anti-fuse FPGA reinforcement protection method for avoiding high-power switching damage of a PIN switch is innovatively provided, and the aim of ensuring the switching reliability realized by an electronic switch in a high-power system is fulfilled so as to meet the application target of aerospace engineering. The design of the scheme can effectively ensure the realization of the lightweight base station, adopts the mode of minimum space navigation engineering cost, and prevents the problem of burning out due to the fact that the electronic switch serving as a single point of the system is in a working condition with high-power signal switching because of abnormal software functions. The reliability of the system is greatly improved, and the occurrence of the situation that the task execution is seriously influenced is avoided. Disclosure of Invention The invention solves the technical problems of overcoming the defects of the prior art, providing a satellite-borne anti-fuse FPGA reinforcement protection method for avoiding the high-power switching damage of a PIN switch, and aiming at ensuring the switching reliability realized by an electronic switch in a high-power system so as to realize the aim of meeting the application of aerospace engineering. The design of the scheme can effectively ensure the realization of the lightweight base station, adopts the mode of minimum space navigation engineering cost, and prevents the problem of burning out due to the fact that the electronic switch serving as a single point of the system is in a working condition with high-power signal switching because of abnormal software functions. The reliability of the system is greatly improved, and the occurrence of the situation that the task execution is seriously influenced is avoided. In order to achieve the above purpose, the technical scheme adopted by the invention comprises the following steps: A satellite-borne anti-fuse FPGA reinforcement protection method for avoiding high-power switching damage of PIN switches comprises the following steps: Generating an original control signal through an SRAM type FPGA, wherein the pulse width of the original control signal is at least the sum of the maximum time delay delta t1 of switching, the radio frequency transmission and stabilization time delta t2, the design margin delta t3 and the time of an effective switching window delta t 4; The original control signal obtains a DA turn-off signal and an effective window signal in an anti-fuse FPGA; the DA off signal is used for turning off the input signal of the DA device for a period of time; The effective window signal cuts off or connects the latch, so that the electro