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CN-121983098-A - RRAM-based memory cell and nonvolatile memory drive circuit

CN121983098ACN 121983098 ACN121983098 ACN 121983098ACN-121983098-A

Abstract

A memory cell based on RRAM and a nonvolatile memory drive circuit are provided, which are composed of a 14T2R-NVSRAM memory cell based on RRAM and a nonvolatile memory drive circuit. The 14T2R-NVSRAM storage unit comprises an SRAM module and an RRAM module, the SRAM module supports quick reading and writing of data, and compared with a traditional 6T-SRAM, a group of control switches are added, so that fault conduction risks between the SRAM module and the RRAM module can be effectively reduced. The RRAM module is used for realizing nanosecond backup and recovery of SRAM data and solving the problem of data loss after power failure. The nonvolatile memory driving circuit comprises a power supply detection circuit and a control signal generation circuit, wherein the power supply detection circuit realizes automatic power-down backup and power-on recovery of data, and the signal generation circuit is responsible for generating control signal waveforms and time sequence control required in the data backup and recovery process.

Inventors

  • Guo Huimang
  • LI YUJIA
  • Dong Chenge
  • Ren Tingrui
  • HAN XUPENG
  • WANG LIANG
  • ZHAO YUANFU

Assignees

  • 北京时代民芯科技有限公司
  • 北京微电子技术研究所

Dates

Publication Date
20260505
Application Date
20251231

Claims (10)

  1. 1. A RRAM-based 14T2R-NVSRAM memory cell, characterized by: the SRAM comprises an SRAM module RRAM module, wherein: The SRAM module executes data reading and writing under the on state, the latch amplifying signal capacity is enhanced by the integrated design control switch transistor, and the SRAM module is used for backing up and recovering independent operation of data under the off state, so that data fault conduction is prevented; The RRAM module is used for controlling a data node Q and a data node QB which are connected with the SRAM module, the RRAM module is connected to a CTRL signal through a TE end of a top electrode and grounded through a BE end of a bottom electrode, and is used for controlling data backup and recovery operation.
  2. 2. The RRAM-based 14T2R-NVSRAM memory cell of claim 1, wherein: the control signals required by the 14T2R-NVSRAM memory cell include BL signals and BLB signals, SRB signals and SR signals, CWL signals, SL and CTRL signals, wherein: BL signal and BLB signal are used as write-in and read-out data channels controlled by WL in SRAM module, SRB signal and SR signal are used for controlling on and off of SRAM module respectively, CWL, SL and CTRL signals are used for implementing data backup and recovery operation of RRAM module, SET process implements independent operation by control signal SL to avoid influence of data backup process on data node voltage of SRAM module.
  3. 3. The RRAM-based 14T2R-NVSRAM memory cell of claim 2, wherein: The SRAM module comprises an SRAM module body, wherein the SRAM module body comprises a PMOS tube P1, a PMOS tube P2, a PMOS tube P3 and a PMOS tube P4, the NMOS tube N1, the NMOS tube N2, the NMOS tube N3, the NMOS tube N4, the NMOS tube N5 and the NMOS tube N6, when a state word SR=1 between the NMOS tube N3 and the NMOS tube N4, a state word SRB=0 between the PMOS tube P1 and the PMOS tube P2, the PMOS tube P1, the PMOS tube P2, the NMOS tube N3 and the NMOS tube N4 are conducted, the SRAM module body normally works and latches data, and when the NMOS tube N5 and the NMOS tube N6 are conducted, the SRAM module body writes data into a data node Q and a data node QB or reads data from the data node Q and the data node QB through a bit line BL/BLB.
  4. 4. The RRAM-based 14T2R-NVSRAM memory cell of claim 2, wherein: The RRAM module comprises an NMOS tube N7, an NMOS tube N8, an NMOS tube N9, an NMOS tube N10, a resistive random access memory RRAM1 and a resistive random access memory RRAM2, and the memory unit further comprises a nonvolatile memory driving circuit.
  5. 5. The RRAM-based 14T2R-NVSRAM memory cell of claim 4, wherein: The data backup comprises a SET operation and a RESET operation, wherein the SET operation applies pulse signals to TE ends of the resistive random access memory RRAM1 and the resistive random access memory RRAM2 from a CTRL end, the SL signals are SET to a high level, the NMOS tube N9 and the NMOS tube N10 are conducted to enable BE ends of the resistive random access memory RRAM1 and the resistive random access memory RRAM2 to BE grounded, the CWL is SET to a low level, and the resistive random access memory RRAM1 and the resistive random access memory RRAM2 are initialized to a low resistance state through the SET operation after the NMOS tube N7 and the NMOS tube N8 are closed; Setting CTRL signals and SL signals to low level in RESET operation to enable TE ends of the resistive random access memory RRAM1 and the resistive random access memory RRAM2 to BE grounded, setting CWL to high level, setting BE ends of the resistive random access memory RRAM1 to BE high level if data stored in the SRAM module is Q=1 and QB=0, enabling the TE ends to BE low level to realize negative voltage difference, switching to high resistance state through RESET operation, enabling no voltage difference to BE generated at two ends of the resistive random access memory RRAM2 to keep low resistance state, and enabling no voltage difference at two ends of the resistive random access memory RRAM1 to keep low resistance state if data stored in the SRAM module is Q=0 and QB=1, and switching the resistive random access memory RRAM2 to high resistance state through RESET operation.
  6. 6. The RRAM-based 14T2R-NVSRAM memory cell of claim 5, wherein: When the nonvolatile storage drive circuit detects that the power supply starts to be powered on from a power-down state or an enable signal EN_restore=1, starting a data recovery operation, and recovering high-resistance state or low-resistance state form data in the RRAM module to a high-level or low-level form of data nodes Q and QB of the SRAM module; The data recovery includes a precharge phase and a recovery phase; In the pre-charging stage, SR is set at a low level, SRB is set at a high level, the SRAM module is closed, WL is set at a high level, and after the NMOS tube N5 and the NMOS tube N6 are conducted, BL signals and BLB signals are both at a high level and charge the Q end and the QB end; In the recovery stage, CWL and SRB are set at low level after precharge, SR is set at high level, the SRAM module works normally and the data recovery is completed after the voltage difference between the Q terminal and the QB terminal is amplified.
  7. 7. A non-volatile memory drive circuit for implementing the 14T2R-NVSRAM memory cell of claim 6, characterized by: The nonvolatile memory driving circuit comprises a power supply monitoring module and a control signal generating module; The power supply monitoring module comprises a voltage-stabilizing diode, a capacitor, a reference voltage source Vref and a comparator, wherein in the power-up process, a VDD power supply charges the capacitor unidirectionally through the voltage-stabilizing diode, the voltage Vcap of the capacitor is continuously increased and lower than that of the VDD power supply, enabling data recovery operation is executed when the voltage of the capacitor is higher than that of the VDD power supply, in the power-down process, the voltage of the VDD power supply is continuously reduced under the influence of the discharging characteristic of the capacitor until the voltage of the capacitor is higher than that of the Vcap-VDD power supply, enabling data storage is executed, and when the power supply monitoring module monitors that the voltage of the VDD power supply is lower than a SET threshold, pulse signals of a CTRL signal and a CWL signal in SET and RESET periods are output so as to realize data backup of the SRAM module.
  8. 8. The nonvolatile memory drive circuit of claim 7 wherein: The control signal generating module outputs all control signals required in the backup and recovery period through a logic gate circuit and a trigger according to the row and column gating signals RowDec/ColDec and the backup and recovery enabling signals EN_store/EN_restore as input, and the control signal generating module and the power monitoring module form a nonvolatile storage driving circuit; In the data backup SET process, CTRL AND SL signals are controlled by row/column driving signals RowDec/ColDec AND a data backup enabling signal EN_store, when row/column selection communication signals AND the data backup enabling signal are simultaneously valid, logic gates AND1 AND AND3 output high levels AND respectively transmit the high levels to J end inputs of JK triggers T1 AND T4, AND the K end is fixed to the high level; in the data backup RESET process, the CWL signal is controlled by the column driving signal ColDec and the en_store signal, and a RESET pulse is generated in the second stage of Store through the flip-flop T4 and the logic and gate, so that the RESET operation is completed.
  9. 9. The nonvolatile memory drive circuit of claim 8 wherein: In the data recovery process, the WL end, the SRB end, the BL end and the BLB end are set to be high level in the precharge stage, the SR end is set to be low level, the SRAM module is closed, the voltage difference between the Q end and the QB end of the data node is formed according to the resistance difference of RRAM at two sides of the nonvolatile memory module, the WL end, the SRB end, the BL end and the BLB end are switched to be low level in the amplifying recovery stage, the SR end is set to be high level, the SRAM module is started, the voltage difference between the Q end and the QB end is recovered to be high level VDD and low level 0 through latch amplification, and the data recovery process is controlled by row/column driving signals RowDec/ColDec and a data recovery enabling signal EN_restore, and signals are output through a logic AND gate and a D trigger.
  10. 10. The nonvolatile memory drive circuit of claim 9 wherein: The memory unit, the nonvolatile memory driving circuit, the address decoder module and the amplifier form a memory architecture, in the memory architecture, a ROW strobe signal ROW_DEC and a column strobe signal COL_DEC are respectively arranged, and corresponding control operation is executed by generating signals required by data backup through the nonvolatile memory driving circuit according to enable signals for data backup and recovery.

Description

RRAM-based memory cell and nonvolatile memory drive circuit Technical Field The invention relates to a memory cell based on RRAM and a nonvolatile memory drive circuit, belonging to the technical field of integrated circuit memories. Background NVSRAM is a nonvolatile Static Random Access Memory (SRAM) combining nonvolatile memory (NVM) and SRAM, and data in SRAM is backed up before system power failure, so as to maintain the read-write speed of SRAM and solve the problem of data volatile. Conventional NVM, such as FLASH, EPROM, EEPROM, etc., are developed based on ROM technology, so that there are common disadvantages of slow read/write speed, special method for programming/erasing, and short lifetime. Compared with the traditional double-macro structure based on the bus, the single-macro structure of the storage node fusion connects the SRAM and the NVM in parallel, and is integrated in the storage unit through the stacking technology, so that efficient parallel data backup and recovery are realized, the area is reduced, the energy consumption is reduced, and the reliability of data backup is ensured. This embedded structure places higher demands on the size of the NVM and compatibility with CMOS. Resistive Random Access Memory (RRAM) is a hot spot of current research due to its simple structure, low power consumption, high speed, good CMOS compatibility and three-dimensional integration potential. Compared with the traditional memory cell, the RRAM realizes data storage through reversible resistance state change, and has smaller cell area and higher integration density. Thus, the application of RRAM cells in NVSRAM memory arrays is expected to significantly improve the overall performance of the memory, particularly in embedded systems and low power devices, showing great potential. Efficient RRAM-based operation is achieved in NVSRAM arrays, and design of the driving circuit is of paramount importance. The memory mechanism of the RRAM determines the strict requirements of the RRAM on the operation voltage, the write timing and the read-write control precision. How to design an efficient and reliable array driving circuit while guaranteeing the performance of the RRAM is a key technical challenge currently faced. Disclosure of Invention Aiming at various defects of the traditional bus-based double-macro structure in the prior art, the invention provides a RRAM-based memory cell and a nonvolatile memory drive circuit. The invention solves the technical problems by the following technical proposal: a RRAM-based 14T2R-NVSRAM memory cell, comprising an SRAM module RRAM module, wherein: The SRAM module executes data reading and writing under the on state, the latch amplifying signal capacity is enhanced by the integrated design control switch transistor, and the SRAM module is used for backing up and recovering independent operation of data under the off state, so that data fault conduction is prevented; The RRAM module is used for controlling a data node Q and a data node QB which are connected with the SRAM module, the RRAM module is connected to a CTRL signal through a TE end of a top electrode and grounded through a BE end of a bottom electrode, and is used for controlling data backup and recovery operation. The control signals required by the 14T2R-NVSRAM memory cell include BL signals and BLB signals, SRB signals and SR signals, CWL signals, SL and CTRL signals, wherein: BL signal and BLB signal are used as write-in and read-out data channels controlled by WL in SRAM module, SRB signal and SR signal are used for controlling on and off of SRAM module respectively, CWL, SL and CTRL signals are used for implementing data backup and recovery operation of RRAM module, SET process implements independent operation by control signal SL to avoid influence of data backup process on data node voltage of SRAM module. The SRAM module comprises an SRAM module body, wherein the SRAM module body comprises a PMOS tube P1, a PMOS tube P2, a PMOS tube P3 and a PMOS tube P4, the NMOS tube N1, the NMOS tube N2, the NMOS tube N3, the NMOS tube N4, the NMOS tube N5 and the NMOS tube N6, when a state word SR=1 between the NMOS tube N3 and the NMOS tube N4, a state word SRB=0 between the PMOS tube P1 and the PMOS tube P2, the PMOS tube P1, the PMOS tube P2, the NMOS tube N3 and the NMOS tube N4 are conducted, the SRAM module body normally works and latches data, and when the NMOS tube N5 and the NMOS tube N6 are conducted, the SRAM module body writes data into a data node Q and a data node QB or reads data from the data node Q and the data node QB through a bit line BL/BLB. The RRAM module comprises an NMOS tube N7, an NMOS tube N8, an NMOS tube N9, an NMOS tube N10, a resistive random access memory RRAM1 and a resistive random access memory RRAM2, and the memory unit further comprises a nonvolatile memory driving circuit. The data backup comprises a SET operation and a RESET operation, wherein the SET operation applies pulse s